MEMS Fabrication Patents: Leaders, Trends & White Space 2026
- Filings peaked in 2019 at 95 and have since flattened, with the 2022 midpoint at 84 — a mature claim landscape rather than an expanding one.
- Wafer level packaging and eutectic bonding dominate the most-cited prior art, meaning new entrants are filing around a small set of foundational bonding and release patents.
- Several major assignees show 0 filings in the latest year with -100% YoY drops, a pattern consistent with publication lag rather than an actual exit from the field.
Filing growth compares 2021 (57 records) with 2024 (29) — a three-year span. 2024 is the most recent year we treat as complete: publication lags filing by roughly 18 months, so 2025 onwards are still filling in and any growth rate that ends there would understate the field. Top-5 share is the combined record count of the five largest assignees divided by all 1,813 records in scope (CR5), not by the ranked leaders only.
What this landscape covers
This dataset tracks patent families addressing sacrificial layer release, stiction, wafer level packaging, resonant frequency control and process integration claims within MEMS fabrication and device architectures, filtered to IPC classes B81C1, B81B3 and H01L21. It spans 1,813 patent families published between 2015 and mid-2026, drawn primarily from US, EPO, WIPO, Chinese, Taiwanese and Australian filings.
Because publication trails filing by roughly 18 months, the last one to two years in any trend understate real filing activity. The patterns below should be read as directional rather than final for 2025 and 2026.
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Filing trends and technology composition
The filing curve and IPC spread together show a field that built out its core packaging and release techniques through the late 2010s and has since settled into incremental claims layered on established bonding and integration methods.
A flattening filing curve
Filings rose from 77 in 2017 to a peak of 95 in 2019, held near that level through the 2022 midpoint of 84, and have tapered since — consistent with a technology area where core architectures are settled and filers are now defending refinements rather than staking new ground.
Concentration in device structure and manufacturing classes
B81B (microstructural devices) and B81C (MEMS manufacturing) carry the largest record counts, with H01L (semiconductor devices) a distant third. The presence of G02B and H01H alongside the core MEMS classes points to steady cross-filing into optical MEMS and switch/relay applications rather than a distinct wave of new activity there.
Shares are the percentage of the 1,813 records in scope. A patent can carry several IPC classes, so the shares add up to more than 100%.
Go deeper on MEMS Fabrication and Devices with Eureka
This page is one run against one query. Ask Eureka your own question about mems fabrication and devices and every answer comes back with the patent numbers behind it.
Try EurekaThe prior art new filings have to clear
Wafer level packaging for MEMS device (US10301171B1)
A microelectromechanical system (MEMS) device with a device substrate carrying a MEMS component between top and bottom bond rings. Top and bottom caps are joined to those bond rings by eutectic bonds, encapsulating the device entirely through the wafer-level bonding structure rather than a subsequent packaging step.Filed by Vanguard International Semiconductor Singapore; granted 2019-05-28.


| # | Publication no. | Patent title | Citations |
|---|---|---|---|
| 1 | US6384353B1 | Micro-electromechanical system device | 386 |
| 2 | US20040016995A1 | MEMS control chip integration | 330 |
| 3 | US20100193884A1 | Method of Fabricating High Aspect Ratio Transducer Using Metal Compression Bonding | 317 |
| 4 | US20030054588A1 | Methods for depositing, releasing and packaging micro-electromechanical devices on wafer substrates | 310 |
| 5 | US20090108381A1 | Low temperature bi-CMOS compatible process for MEMS RF resonators and filters | 279 |
| 6 | US5919548A | Chemical-mechanical polishing of recessed microelectromechanical devices | 277 |
| 7 | US6379988B1 | Pre-release plastic packaging of MEMS and IMEMS devices | 274 |
| 8 | US6245590B1 | Frequency tunable resonant scanner and method of making | 274 |
| 9 | US20030036215A1 | MEMS device made of transition metal-dielectric oxide materials | 244 |
| 10 | US9394161B2 | MEMS and CMOS integration with low-temperature bonding | 243 |
Citation counts reflect influence within this searched corpus and skew toward older filings; they are not a measure of current commercial relevance.
Each row carries its publication number; clicking a row searches Eureka by that number.
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Three patterns stand out once the trend and citation data are read together: a matured filing curve, a packaging-heavy citation base, and a receiving-office mix that is still overwhelmingly US-centred.
The curve has already crested
Filings peaked in 2019 and the 2022 midpoint of 84 shows no renewed acceleration. Combined with publication lag, this looks like a technology area consolidating around known architectures rather than one drawing fresh entrants.
Bonding and release patents anchor the field
The most-cited records concern wafer-substrate release methods and eutectic/metal-compression bonding. Any new packaging or release claim is filed in the shadow of these, which raises the bar for novelty in that specific sub-area.
Filing is still concentrated in the US
The receiving-office split shows the United States taking roughly six times the volume of the next-largest office, EPO. China's 71 filings are comparatively modest for a semiconductor-manufacturing category, suggesting the competitive center of gravity for MEMS process patents remains US-anchored.
Eureka can read the same corpus for gaps instead of for coverage: under-claimed branches adjacent to mems fabrication and devices, with the prior art for and against each one.
Who holds the claim space
Filing activity concentrates among a handful of semiconductor and MEMS-focused assignees, several of which show 0 filings in the latest recorded year — a pattern that publication lag makes hard to read as an actual pullback.
One assignee dominates internal co-filing
Of the 10 identified co-assignee pairs in this dataset, the strongest link — 13 shared filings between a single MEMS-focused assignee and one inventor — is roughly 1.4 times the next-strongest pair, pointing to a concentrated internal inventing team rather than broad external collaboration.
Multiple established filers show zero latest-year activity
Several long-standing assignees in this space report 0 filings in the most recent year with -100% year-over-year change. Given the roughly 18-month lag between filing and publication, this is more likely an artifact of the data cut-off than evidence these firms have stopped filing.
Device-structure claims outnumber process claims
B81B (microstructural devices) carries more records than B81C (MEMS manufacturing), meaning the dataset skews toward device architecture claims rather than pure fabrication-process claims — useful context when scoping a freedom-to-operate search toward one or the other.
| Assignee | Recent year | YoY |
|---|---|---|
| Taiwan Semiconductor Manufacturing Company (TSMC) | 0 | -100% |
| InvenSense, Inc. | 0 | -100% |
| Texas Instruments Incorporated | 0 | -100% |
| Qualcomm MEMS Technologies, Inc. | 0 | — |
| Honeywell International Inc. | 0 | — |
| Analog Devices, Inc. | 0 | — |
| Freescale Semiconductor, Inc. | 0 | — |
| Infineon Technologies AG | 0 | -100% |
Where to take this next
The dataset points to a field with settled core architectures and a handful of thinner branches. Two directions follow from that.
Map the bonding and release claim boundaries
Given how heavily the most-cited records concentrate on wafer-substrate release and eutectic bonding, a detailed claim chart against those specific families is the fastest way to find where a new packaging approach actually differs.
Explore prior art in EurekaWatch for re-emerging filing activity
Because the latest one to two years understate true filing volume, re-check the trend in six to twelve months before concluding the field has genuinely gone flat.
Track filing trends in EurekaCommon questions on MEMS fabrication patents
Most claims in this dataset cover either a device structure — the microstructural elements captured under IPC class B81B — or a manufacturing step under B81C, such as sacrificial layer release, wafer bonding, or packaging sequence. A single filing often combines both, describing a device architecture together with the specific process steps used to build and seal it. Reading the independent claims first will usually tell you whether the patent is structure-limited or process-limited, which matters for design-around work.
The most-cited records in this corpus, including patents on metal compression bonding and eutectic bond encapsulation, established foundational methods for sealing a MEMS device at the wafer stage rather than after dicing. Later filings routinely cite these because nearly any wafer-level packaging approach has to address the same bonding and hermeticity problems. High citation counts here reflect that foundational role, not that the underlying technology is still cutting-edge — citation counts in a fixed corpus naturally favour older filings.
Based on this dataset, filings rose from 77 in 2017 to a peak of 95 in 2019, held near 84 by the 2022 midpoint, and have declined since. That said, publication typically lags filing by about 18 months, so the drop shown in the most recent one to two years is partly an artefact of records not yet being published, not necessarily a real collapse in filing activity. The honest read is a mature, flattening field rather than a rapidly growing or a genuinely dying one.
This dataset's assignee ranking is dominated by established semiconductor and MEMS manufacturers, several of which show zero filings in the latest recorded year with -100% year-over-year change — a pattern best explained by publication lag rather than these firms exiting the space. Co-assignee data also shows one MEMS-focused assignee with notably deep internal co-filing links to specific inventors, suggesting a concentrated core R&D team rather than broad external partnering. Specific rankings are best read directly from the assignee table rather than summarised here, since positions shift as more recent filings publish.
Relative to the dense claim territory around wafer-level packaging and bonding, sub-areas such as sub-micron stiction coatings, RF MEMS resonator temperature compensation, and bi-CMOS compatible low-temperature process integration show thinner filing density in this dataset. That does not guarantee those areas are easy to patent in, but it does mean fewer blocking claims to search through before filing. Any white space assessment should still be paired with a full freedom-to-operate search, since low filing density can also just mean an area has not yet found a commercial application.
B81B covers microstructural devices — the MEMS component or device structure itself — while B81C covers the manufacturing and fabrication processes used to build MEMS devices, such as sacrificial layer release or wafer-level integration steps. In this dataset B81B carries more records than B81C, meaning device-structure claims outnumber pure process claims. A filing can sit in both classes at once if it claims a novel structure produced by a novel process.
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Disclaimer. This page is generated from Patsnap Eureka data drawn from a limited snapshot of global patent and scientific-literature records, and is provided for general information and reference only.
Patent data carries inherent limitations: recent filings (typically the most recent 18–24 months) are under-counted due to standard publication lag; counts may be reported at either a patent-family or a patent-record basis and are not always directly comparable; classification, applicant-name, and citation data may contain errors, duplicates, or omissions; and the underlying search query defines and constrains the scope shown. As a result, the analysis may be incomplete or inaccurate and may not reflect the full technology landscape.
Nothing on this page constitutes an exhaustive prior-art, novelty, freedom-to-operate, or validity search, nor does it constitute legal, financial, investment, or professional advice, and it should not be relied upon as such. Any patent, commercial, or strategic decision should be verified independently and reviewed with qualified patent, legal, and domain professionals. Patsnap makes no warranties, express or implied, as to the accuracy, completeness, or fitness for any particular purpose of the information presented.
Machine translation. Assignee and organisation names originally recorded in Chinese, Japanese or Korean have been rendered into English by an AI translation step so that the tables stay readable. These renderings are best-effort and may not match a company’s registered English name; the original name is what the underlying patent record carries, and it is what any Eureka query launched from this page uses.