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MPC vs PID Control for Semiconductor Stages — PatSnap Eureka

MPC vs PID Control for Semiconductor Stages — PatSnap Eureka
Semiconductor Motion Control

MPC vs. PID Control for High-Precision Semiconductor Motion Stages

Based on 50+ patents spanning 1995–2026, this analysis examines why classical PID control's causal lag is structurally insufficient for sub-micrometer semiconductor positioning — and how Model Predictive Control and hybrid architectures resolve it.

MPC vs PID Control Architecture: MPC uses prediction horizon + constrained optimization; PID uses Kp·e(n) + ΣKi·e(j) + Kd·(e(n)−e(n−1)) Schematic comparison of MPC and PID control loops for semiconductor motion stages. MPC predicts future states over a horizon and solves a constrained optimization problem each cycle; PID reacts to current error only. Source: PatSnap Eureka patent analysis. PID CONTROL Reactive — error driven u(n) = Kp·e(n) + ΣKi·e(j) + Kd·Δe No future state prediction No native constraint handling MPC CONTROL Predictive — horizon-based min J = Σ||x−ref||²Q + ||u||²R Predicts N steps ahead Enforces actuator + position limits VS HYBRID ARCHITECTURE (Dominant Industrial Solution) Outer loop: MPC trajectory planning (slow cycle) Inner loop: PID fast disturbance rejection Omron 2020, 2023 · Nanjing Univ. 2012
50+
Patents analyzed (1995–2026)
±10%
Plant model deviation MPC tolerates while maintaining vibration suppression
3
Core architectural themes: PID, MPC, Hybrid
2026
Latest hybrid feedforward-feedback patents (Suzhou Maiwei)
PID Control

PID: The Dominant Baseline — and Its Structural Limits

PID (Proportional-Integral-Derivative) control remains the dominant baseline technology for servo motion stages in semiconductor manufacturing. Its output is calculated as a linear combination of the current error, the accumulated error integral, and the error rate of change: u(n) = Kp·e(n) + ΣKi·e(j) + Kd·(e(n)−e(n−1)), as described by Beijing Hongzhi Diantong Technology (2017). Kp provides immediate proportional response, Ki eliminates steady-state error, and Kd anticipates error trend through differentiation.

The fundamental problem for semiconductor stages is causal lag. As documented by the Chinese Academy of Sciences Institute of Microelectronics (2022), classical PID "cannot pre-judge changes in tracking position, cannot obtain ideal tracking accuracy, and cannot make predictions for errors that will occur in the future." The control input calculated for the current error will only affect future tracking error — a mismatch that prevents the technique from meeting precision requirements in silicon wafer surface tracking.

In semiconductor packaging equipment, the conflict between speed and precision is acute. As detailed by Dongguan Pulaixun Intelligent Technology (2022), miniaturized multi-pin chips demand that the motion platform reach a target position within extremely short periods with simultaneous high acceleration and high accuracy — a contradiction PID alone struggles to resolve, as high acceleration extends settling time and degrades positioning accuracy.

Further complicating PID deployment is parameter sensitivity. Kyocera (2006) notes that PID parameters P, I, and D must be determined experimentally in advance for each hardware configuration; when drive characteristics change due to friction member wear or preload fluctuation, the fixed PID parameters cannot respond, causing positioning degradation mid-operation. This requirement for upfront empirical tuning makes PID less robust in production environments where mechanical properties shift over the machine's lifetime. Learn more about patent landscape analytics for servo control technologies.

3
Gain constants (Kp, Ki, Kd) — fixed over full operating range
~0
Predictive horizon — purely reactive to past and present error
None
Native constraint enforcement on velocity, acceleration, or jerk
High
Sensitivity to plant parameter changes (wear, thermal shift)
  • Trivial computational cost — 3 multiplications + 2 additions per cycle
  • Well-understood tuning procedures with auto-tuning tool support
  • Requires only 3 gain constants for configuration
  • Widely deployed across all servo motion stage types
Model Predictive Control

MPC: Predictive Horizon, Constraint Handling, and Semiconductor Stage Applications

MPC differs from PID at its architectural foundation — maintaining an internal dynamic model, predicting future states, and solving a constrained optimization problem at every control cycle.

Predictive Architecture

Two-Tier Hierarchical Control Structure

Omron's 2020 patent describes a first processing unit running MPC at a slower outer cycle to generate servo commands, and a second processing unit running conventional feedback control at a faster inner cycle. This hierarchical structure explicitly separates the predictive planning layer from the reactive execution layer — a design pattern adopted across the industry.

Omron Corporation, 2020
Semiconductor Application

Silicon Wafer Surface Tracking Without Lag

The Chinese Academy of Sciences (2022, 2024) applies MPC specifically to silicon wafer surface height tracking, where the unknown and dynamically varying surface profile makes PID's reactive lag particularly costly. The MPC controller uses historical position data from multiple past time steps together with position input commands to generate both prediction data and compensation data — proactively estimating and counteracting future errors.

CAS Institute of Microelectronics, 2022
Constraint Handling

Simultaneous Enforcement of All Physical Limits

Huazhong University of Science and Technology (2023) explicitly compares MPC and PID: PID cannot simultaneously achieve the desired steady-state response and the specific dynamic transient profile (slow start, fast middle, slow end) required by gear drive systems. MPC enforces both trajectory constraints and dynamic shaping objectives through the constrained optimization problem — making it inherently more robust to gear backlash uncertainty than conventional PID compensation strategies.

Huazhong University, 2023
Vibration Suppression

Robust Performance Under Plant Model Uncertainty

Omron's 2024 simulation results demonstrate that mode-switched MPC configured with a 9.2 Hz natural frequency object maintains anti-vibration performance even when the actual resonant frequency deviates −10% (to 8.28 Hz) from the modeled value. A pure model-based open-loop approach fails under the same perturbation, illustrating MPC's greater robustness to plant model uncertainty compared to fixed-gain PID.

Omron Corporation, 2024 — ±10% model error tolerance
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Patent Data Analysis

Visualising the MPC vs. PID Technology Landscape

Key data points from the 50+ patent dataset, spanning assignee activity, architectural themes, and performance dimensions.

Key Assignee Patent Activity in MPC/PID Motion Control

Omron is the most prolific assignee in MPC-for-servo, with patents spanning 2017–2024. CAS Institute of Microelectronics leads in semiconductor-specific MPC applications.

Key Assignee Patent Activity: Omron 6 patents, CAS Microelectronics 2, Mitsubishi Electric 2, Nanjing Univ 1, Dongguan Pulaixun 2, Applied Materials 1, Canon 1, Huazhong Univ 1 Bar chart showing relative patent activity by key assignee in MPC and PID motion control for semiconductor stages, based on PatSnap Eureka analysis of 50+ patents from 1995–2026. Omron leads with the broadest portfolio of hierarchical MPC-servo architectures. 6 5 4 3 2 1 6 Omron 2 CAS IME 2 Mitsubishi 2 Pulaixun 1 Nanjing U 1 Appl. Mat. 1 Canon Patent Count

MPC vs. PID: Capability Dimension Comparison

Relative capability scores across five critical dimensions for semiconductor motion stage control, derived from patent literature analysis.

MPC vs PID Capability Comparison: Tracking Latency MPC 9/10 PID 2/10; Constraint Handling MPC 10/10 PID 1/10; Robustness to Plant Change MPC 8/10 PID 3/10; Computational Cost MPC 2/10 PID 10/10; Config Simplicity MPC 2/10 PID 9/10 Horizontal paired bar chart comparing MPC and PID across five capability dimensions for semiconductor motion stage control. MPC leads on tracking, constraints, and robustness; PID leads on computational cost and configuration simplicity. Source: PatSnap Eureka patent analysis. MPC PID Tracking Latency 9/10 2/10 Constraint Handling 10/10 1/10 Robustness to Plant Change 8/10 3/10 Computational Cost (lower=better) 2/10 10/10 Configuration Simplicity 2/10 9/10 Source: PatSnap Eureka — Patent literature analysis, 2022–2024

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Head-to-Head Analysis

MPC vs. PID: Five Critical Dimensions for Semiconductor Stages

A direct comparison across tracking latency, constraint awareness, robustness, computational demand, and configuration complexity — all documented in the patent literature.

Dimension MPC PID Patent Evidence
Tracking Latency Predictive — computes control from predicted future states ADVANTAGE Reactive — error must manifest before correction begins LAG CAS IME, 2022 — "cannot pre-judge changes in tracking position"
Constraint Handling Native — enforces position, velocity, acceleration, jerk simultaneously ADVANTAGE None native — constraints imposed exogenously via trajectory generation Huazhong Univ, 2023; Nanjing Univ, 2012
Robustness to Plant Change High — maintains performance at ±10% model frequency deviation ADVANTAGE Low — fixed gains degrade when bearing preload or stiffness shifts Omron, 2024 — 9.2 Hz → 8.28 Hz deviation test
Computational Demand High — constrained QP solve required at each control cycle Negligible — 3 multiplications + 2 additions per cycle ADVANTAGE Beijing Hongzhi, 2017; Mitsubishi Electric, 2024
Configuration Complexity High — requires validated state-space model, prediction horizon, weighting matrices, constraint definitions Low — 3 gain constants, empirical tuning, auto-tuning tool support ADVANTAGE Nanjing Univ, 2012 — "difficult to satisfy real-time requirements"
🔒
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Omron 2-processor Nanjing composite mode MRAC-PID switching + more
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Industry Convergence

Hybrid MPC+PID: The Dominant Industrial Solution

The predominant practical outcome of the MPC-vs-PID comparison is that industry solutions are converging on hybrid architectures that exploit the complementary strengths of each paradigm.

🏗️

Omron Two-Processor Architecture (2020, 2023)

A first processor runs MPC at a long cycle (tens to hundreds of milliseconds) to generate optimal servo trajectory commands, while the second processor executes fast-cycle PID-based feedback control at the actuator level. The MPC layer handles constraint satisfaction and optimal trajectory planning; the PID layer handles fast disturbance rejection at the actuator interface where low latency is critical.

🔬

Nanjing University Composite Mode Control (2012)

MPC is used as the main servo controller for optimal trajectory tracking, while nonlinear adaptive fuzzy PID is used as the error compensation controller to improve robustness. The MPC control inputs are fed to both the plant and the predictive model; the divergence between predicted and actual outputs drives the fuzzy-PID compensator. This architecture achieves trajectory shaping and constraint satisfaction of MPC together with the low-computation-overhead robustness of PID.

🔒
Unlock 2025–2026 Adaptive Hybrid Strategies
Access the latest MRAC-PID switching and gradient-descent feedforward adaptation patents — the cutting edge of semiconductor motion control.
Suzhou Maiwei 2026 Beijing Univ Aero 2025 + more
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Innovation Landscape

Key Players and Institutional Specialization

Omron Corporation is the most prolific assignee in the MPC-for-servo domain, with multiple patents covering hierarchical MPC-feedback architectures (2020, 2023, 2024), sliding-mode/PID switching (2017, 2020), and surface-following MPC (2024). Omron clearly positions MPC as the successor architecture to classical servo control in precision equipment. Their portfolio is tracked in real time via PatSnap Analytics.

Mitsubishi Electric focuses on computational tractability of MPC for machine tools, with patents on redundant-actuator motion control and mixed-integer MPC with recursive prediction and iterative correction (2024). Their approach fixes a subset of discrete variables using a pre-trained parametric function, converting a computationally intractable mixed-integer problem to a tractable convex program.

Chinese Academy of Sciences – Institute of Microelectronics holds the most focused patents on MPC for semiconductor wafer-stage applications, explicitly comparing MPC to PID in the context of silicon wafer surface tracking (2022, 2024). These are the primary patents establishing MPC's superiority for non-stationary surface profiling tasks. The IEEE has published extensively on related model-based servo control theory.

Applied Materials addresses process-level adaptive control in semiconductor manufacturing using machine-learning-based models rather than servo-level MPC (2023), representing the higher-level process control dimension of the same underlying challenge. Canon contributes stage device patents targeting drive profile optimization for substrate processing (2025), reflecting the lithography equipment application domain. For enterprise IP strategy across these assignees, see PatSnap customer case studies.

The innovation trend is clear: the field is moving from monolithic PID loops toward layered architectures where MPC provides the outer trajectory optimization layer and fast feedback provides the inner disturbance rejection layer, with online adaptation to handle non-stationarities that neither classical approach can manage alone. WIPO data confirms the acceleration of precision motion control patent filings from Asian assignees since 2020.

Patent Theme Distribution

Three dominant themes across 50+ patents in the dataset.

Patent Theme Distribution: Classical PID servo architectures ~40%, MPC applied to servo/motion stages ~35%, Hybrid composite MPC+PID strategies ~25% Donut chart showing the three dominant technical themes across 50+ patent records in the semiconductor motion stage control dataset analyzed via PatSnap Eureka. PID architectures remain the largest single theme but hybrid and MPC-specific patents are growing. 50+ Patents
Classical PID (~40%)
MPC Applications (~35%)
Hybrid MPC+PID (~25%)
Summary

Key Takeaways from the Patent Literature

Seven conclusions drawn directly from 50+ patents spanning 1995–2026, covering PID limitations, MPC advantages, and the hybrid convergence trajectory.

PID Limitation

Causal Lag is PID's Fundamental Structural Deficiency

PID can only respond to errors that have already occurred, making it structurally unable to pre-compensate for known trajectory changes or predictable disturbances. This is explicitly documented for silicon wafer surface tracking by the Institute of Microelectronics, CAS (2022).

CAS IME, 2022
MPC Advantage

MPC Provides Constraint-Aware Optimal Trajectory Execution

By solving a constrained optimization problem over a future prediction horizon at each control cycle, MPC simultaneously enforces position accuracy, velocity/acceleration limits, and mechanical safety constraints within a single unified framework, as demonstrated by Huazhong University of Science and Technology (2023).

Huazhong University, 2023
MPC Barrier

Computational Cost Remains MPC's Primary Adoption Barrier

Mitsubishi Electric's recursive-prediction, iterative-correction approach (2024) and Omron's dual-processor hierarchical architecture (2020) represent the state-of-the-art industrial approaches to making MPC computationally tractable for real-time servo control at semiconductor stage update rates.

Mitsubishi Electric, 2024
Industry Direction

Hybrid MPC+PID Architectures Are the Dominant Industrial Solution

The outer MPC layer performs constraint-satisfying trajectory planning, while the inner PID (or sliding-mode) layer handles fast-cycle actuator-level disturbance rejection, as documented in Omron (2023) and Nanjing University of Aeronautics and Astronautics (2012).

Omron, 2023 · Nanjing Univ, 2012
Semiconductor Specific

Sub-Micrometer Packaging Equipment Has Outgrown Pure PID

As demonstrated by Dongguan Pulaixun (2022), even heavily augmented PID with feedforward and disturbance observer requires careful architectural extension to meet the conflicting demands of high acceleration, short settling time, and nanometer-level precision in semiconductor packaging stages.

Dongguan Pulaixun, 2022
Robustness

MPC Maintains Performance Under ±10% Plant Model Error

Omron's simulation results (2024) show that mode-switched MPC maintains vibration suppression performance when the actual resonant frequency deviates 10% from the model value (9.2 Hz → 8.28 Hz), while open-loop model-only control fails under the same condition. Fixed-gain PID offers no equivalent tolerance mechanism.

Omron, 2024 — ±10% model deviation
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References

  1. 用于精密运动平台的模型预测运动控制方法及其系统 — Institute of Microelectronics, Chinese Academy of Sciences, 2022
  2. 用于精密运动平台的模型预测运动控制方法及其系统 (Update) — Institute of Microelectronics, Chinese Academy of Sciences, 2024
  3. 控制系统 — Omron Corporation, 2020
  4. 控制系统 — Omron Corporation, 2023
  5. 控制装置以及存储介质 — Omron Corporation, 2024
  6. 控制系统及记录介质 — Omron Corporation, 2024
  7. 控制装置以及控制方法 — Omron Corporation, 2017
  8. 控制装置以及控制方法 — Omron Corporation, 2020
  9. 基于齿隙死区模型的双电机预测速度控制装置和方法 — Huazhong University of Science and Technology, 2023
  10. 多轴联动数控系统运动平稳性和轮廓加工精度控制方法 — Nanjing University of Aeronautics and Astronautics, 2012
  11. 一种半导体封装控制系统的控制方法 — Dongguan Pulaixun Intelligent Technology, 2022
  12. 一种控制电机的硬件自适应PID控制器及其控制方法 — Beijing Hongzhi Diantong Technology, 2017
  13. 用于混合整数最优控制的快速解的循环预测和迭代校正方法 — Mitsubishi Electric, 2024
  14. 设备运动复合控制方法、装置、计算机设备、存储介质和计算机程序产品 — Suzhou Maiwei Technology, 2026
  15. 一种基于自适应MRAC和PID的分段线性运动控制方法 — Beijing University of Aeronautics and Astronautics, 2025
  16. WIPO — World Intellectual Property Organization — Global patent filing statistics and semiconductor technology trends
  17. IEEE — Institute of Electrical and Electronics Engineers — Model predictive control and servo system technical publications
  18. Chinese Academy of Sciences — Institute of Microelectronics research on precision motion stage control

All data and statistics on this page are sourced from the references above and from PatSnap's proprietary innovation intelligence platform.

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