A nanosheet transistor is a gate-all-around (GAA) field-effect transistor built from stacked horizontal semiconductor sheets, with the gate wrapped fully around each sheet rather than on three sides as in a FinFET. In patent terms this shows up as a distinct wave of filings from around 2017 onward that reuse FinFET-era dielectric and work-function language but add structural claims around stacked sheets, sub-fin isolation, and wrapped source-drain contacts. Searches combining "gate-all-around" or "nanosheet FET" with high-k dielectric and work-function metal terms, as used for this dataset, capture that transition cleanly. The distinction matters for freedom-to-operate work because FinFET-era dielectric patents can still apply to nanosheet implementations even though the structural claims differ.

Cumulative filing leadership in this corpus concentrates among a small group of large semiconductor manufacturers and research-linked entities, including IBM, TSMC, Intel, Samsung, Applied Materials, and several others, alongside university and interuniversity research centres. However, cumulative leadership and current activity diverge sharply here: most of the historically largest filers show zero filings in the most recent year. Anyone assessing "who leads" should separate historical filing volume from current momentum, since they point to different answers in this dataset.

Filings in this corpus peaked at 162 in 2019 and have declined fairly steadily since, reaching 4 in the still-partial most recent year. This pattern is more consistent with the core structural and dielectric claim space having been staked out early than with declining industry interest in the underlying technology, which continues to be central to advanced logic roadmaps. Recent-year counts should also be read with the general 18-month publication lag in mind, which understates the true count for the last one to two years. Even accounting for that lag, the multi-year decline from the 2019 peak through the 2022 midpoint is a real trend, not a lag artefact.

US10692985B2, assigned to International Business Machines Corporation, covers a method of fabricating a gate-all-around FET that forms a stack of silicon nanosheets, adds an interfacial layer, deposits a high-k dielectric conformally, and then performs a reliability anneal after depositing a silicon nitride layer specifically to crystallise the high-k dielectric. It is a process claim tied to that anneal sequence rather than a broad structural claim on nanosheet transistors generally. New filings that use a different dielectric-crystallisation approach, a different anneal sequence, or that skip the SiN capping step before anneal would sit outside its narrowest claims, though a full claim chart is needed before relying on that distinction.

The classification data shows real but comparatively thin overlap between core gate-all-around filings and both nanotechnology-application classification (81 records) and organic-semiconductor classification (20 records), suggesting 2D channel material integration and organic-semiconductor crossover with GAA structures remain less densely claimed than the core dielectric and structural space. Sub-fin isolation schemes and work-function metal tuning for multi-threshold stacks also appear as active but not saturated areas based on the most-cited records. Any white-space claim in these areas should still be checked against the specific cited patents in the relevant IPC subclass, since "less dense" is not the same as "open."