Nanosheet Transistor CMP Patents: Leaders & White Space 2026
- Filing has already peaked. 2019 was the high point at 8 families; the 2022 midpoint sits at only 2, and the trend line is flat to declining, not accelerating.
- A small set of foundational filings carries most of the citation weight. The top-cited record has 115 citations versus 30 for the fifth-ranked record — influence is concentrated in a handful of early inner-spacer and gate-formation disclosures.
- Momentum has stalled across every tracked assignee. Every major filer in this set — logic, memory and equipment names alike — shows zero filings in the latest tracked year, including a -100% YoY drop for one leading foundry.
Filing growth compares 2021 (2 records) with 2024 (3) — a three-year span. 2024 is the most recent year we treat as complete: publication lags filing by roughly 18 months, so 2025 onwards are still filling in and any growth rate that ends there would understate the field.
What this landscape covers
This dataset tracks patent families at the intersection of nanosheet and gate-all-around (GAA) transistor architectures and chemical mechanical planarization — the polishing step that flattens inner-spacer, gate-metal and channel-release structures between process modules. The search combines architecture terms (nanosheet transistor, gate-all-around, nanosheet FET) with CMP-specific language and IPC codes covering planarization apparatus and semiconductor device fabrication, so it captures claims where CMP is integral to forming the nanosheet stack rather than a generic back-end polish step.
Coverage runs from 2015 through the mid-2026 data cut-off. Because publication typically lags filing by around 18 months, the last one to two years in any chart will look thinner than they eventually turn out to be — a real slowdown is visible well before that lag effect could explain it.
Filing trend and technology composition
Two views of the same 35 families: how filing activity has moved year over year, and which classification codes the claims actually sit under.
Filings by year
Activity opened at 4 families in 2017, rose to a peak of 8 in 2019, and had fallen back to 2 by the 2022 midpoint. No year since has shown a rebound, and the most recent tracked year shows zero filings — read with the usual publication-lag caveat, but consistent across multiple consecutive years rather than a single blip.
IPC subclass distribution
Every record sits under H01L (semiconductor devices generally), with the H10D and H10P subclasses — the newer device-level classifications — covering roughly half and a third of the set respectively. Only 2 records touch memory-device manufacture (H10B) and just 1 touches nanotechnology applications (B82Y), indicating the claims are overwhelmingly logic-process oriented rather than memory- or materials-science oriented.
Shares are the percentage of the 35 records in scope. A patent can carry several IPC classes, so the shares add up to more than 100%.
Go deeper on Nanosheet Transistor Chemical Mechanical Planarization with Eureka
This page is one run against one query. Ask Eureka your own question about nanosheet transistor chemical mechanical planarization and every answer comes back with the patent numbers behind it.
Try EurekaThe most-cited filings in this set
Forming a hybrid channel nanosheet semiconductor structure
A method for fabricating a nanosheet semiconductor structure includes forming a first nanosheet field effect transistor (FET) structure having a first inner spacer comprised of a first material and a second nanosheet FET structure having second inner spacer comprised of a second material. The first material is different than the second material. The first nanosheet FET structure is formed by creating a first inner spacer formation within a first silicon germanium (SiGe) channel, wherein the first SiGe channel is comprised in a first channel region of a first FET region. The second nanosheet FET structure is formed by creating a second inner spacer formation within a second SiGe channel.Filed by Adeia Semiconductor Solutions LLC, published 2018-11-08.
| # | Publication no. | Patent title | Citations |
|---|---|---|---|
| 1 | US20190181224A1 | Formation of self-limited inner spacer for gate-all-around nanosheet fet | 115 |
| 2 | US20200006356A1 | Gate formation scheme for nanosheet transistors having different work function metals and different nanosheet… | 61 |
| 3 | US20200043808A1 | Gate-all-around fets having uniform threshold voltage | 50 |
| 4 | US9704863B1 | Forming a hybrid channel nanosheet semiconductor structure | 46 |
| 5 | US20200373206A1 | Gate structures for semiconductor devices | 30 |
| 6 | US10014372B1 | Vertical gate-all-around transistor with top and bottom source/drain epitaxy on a replacement nanowire, and m… | 21 |
| 7 | US20210098588A1 | Gate-All-Around Device with Protective Dielectric Layer and Method of Forming the Same | 18 |
| 8 | US20190393306A1 | Formation of self-limited inner spacer for gate-all-around nanosheet fet | 17 |
| 9 | US10553679B2 | Formation of self-limited inner spacer for gate-all-around nanosheet FET | 14 |
| 10 | US20200083221A1 | Co-integrated channel and gate formation scheme for nanosheet transistors having separately tuned threshold v… | 9 |
Citation counts are drawn from the same searched corpus and favour earlier filings; treat them as a signal of influence on later claim drafting, not as a ranking of current commercial importance.
Each row carries its publication number; clicking a row searches Eureka by that number.
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Browse MCP servers →What the numbers say about this field
Three read-outs from the trend and citation data that matter more than the raw family count.
Activity peaked early and has not recovered
The peak year of 8 families in 2019 was followed by a steady decline to 2 by 2022, with the latest tracked year showing none at all. This is a mature, front-loaded filing wave rather than an emerging one.
Influence sits with a handful of early disclosures
The leading record on inner-spacer formation carries more than double the citations of the next entries, and the gap widens further down the list. New filers are drafting around a small set of foundational claims, not a broad prior-art field.
Claims cluster on logic-process classifications
Nearly all records fall under general semiconductor-device classes rather than memory or nanotechnology-specific codes, confirming this is a logic-fabrication problem — CMP control at the nanosheet gate and spacer level — rather than a materials or memory play.
Filing activity is almost entirely US-routed
Only one record entered via the WIPO/PCT route, meaning nearly all applicants in this set are protecting directly in the US rather than building a multi-jurisdiction family — worth checking before assuming global freedom to operate.
Eureka can read the same corpus for gaps instead of for coverage: under-claimed branches adjacent to nanosheet transistor chemical mechanical planarization, with the prior art for and against each one.
Who is filing, and who has stopped
A small group of logic foundries, an IDM, and equipment suppliers account for the bulk of this set. What stands out is not who leads, but that none of them have filed in the latest tracked year.
Every tracked assignee shows zero in the latest year
Logic foundries, an IDM and an equipment supplier all report zero filings in the most recent tracked year, with one leading foundry showing a -100% year-over-year drop. Read alongside the 18-month publication lag, but the pattern spans several assignees at once rather than one company's pause.
Filing is almost entirely solo
Only one co-assignee pairing appears in this set, linking two affiliated manufacturing entities of the same corporate group. Co-filing across unrelated organisations is essentially absent here.
A compact, concentrated filer set
With only 35 families across the entire search window, this is a narrow field compared to broader GAA-transistor searches — the claim space is occupied by relatively few organisations rather than a long tail of small filers.
| Assignee | Recent year | YoY |
|---|---|---|
| International Business Machines Corporation (IBM) | 0 | — |
| Taiwan Semiconductor Manufacturing Company, Ltd. (TSMC) | 0 | -100% |
| Intel Corporation | 0 | — |
| Applied Materials, Inc. | 0 | — |
| Semiconductor Manufacturing International (Beijing) Corporation (SMIC Beijing) | 0 | — |
| Semiconductor Manufacturing International (Shanghai) Corporation (SMIC Shanghai) | 0 | — |
Where to take this analysis
The trend and assignee patterns raise questions that a static table cannot answer on its own.
Check freedom to operate against the top-cited claims
The citation concentration around a handful of inner-spacer and gate-formation filings means any new process route should be checked against those specific claim sets first.
Explore claims in EurekaTrack whether the filing slowdown reverses
Zero filings in the latest year across every major assignee could mean the technology has settled on standard approaches, or that filings are still working through the publication lag.
Set up monitoring in EurekaMap the under-claimed branches against your roadmap
Thin coverage in areas like post-CMP defect detection or slurry selectivity for SiGe removal may reflect genuine open space rather than lack of interest.
Run a white space search in EurekaCommon questions about this landscape
Chemical mechanical planarization flattens layers between process steps so that subsequent lithography and deposition can proceed on a uniform surface. In nanosheet and gate-all-around transistors, CMP is used after inner-spacer formation, replacement-metal-gate fill, and channel-release steps, where even small topography variation can affect threshold voltage uniformity across stacked channels. This dataset specifically captures filings where CMP is integral to forming the nanosheet stack, not generic back-end-of-line polishing.
The filing trend shows a peak of 8 families in 2019 falling to 2 by 2022 and to zero in the most recent tracked year. This pattern is consistent with an early wave of foundational filings around inner-spacer and gate-formation methods being largely settled, with newer work either building on those claims incrementally or shifting to adjacent architectures like forksheet and CFET. Some of the most recent apparent decline is likely overstated because publication lags filing by roughly 18 months, but the multi-year downward slope predates that window.
The tracked assignee set includes major logic foundries, at least one IDM, and equipment suppliers, reflecting that CMP process claims for nanosheet transistors sit at the intersection of chip design and fab equipment. Every one of these assignees shows zero filings in the latest tracked year, including a -100% year-over-year drop for one leading foundry, which points to a broadly synchronized slowdown rather than one company pulling back. Co-filing between unrelated organisations is rare in this set — only one co-assignee pairing appears, and it links two affiliated entities of the same corporate group.
Coverage is thin in post-CMP defect detection for released nanosheet channels, CMP slurry selectivity tuned for SiGe sacrificial layer removal, and planarization endpoint control specifically at the inner-spacer formation step. Coverage of CMP integration for stacked forksheet or CFET structures is also sparse relative to standard nanosheet architectures. These are the sub-areas worth a dedicated freedom-to-operate and novelty check before committing R&D resources, since thin filing counts can reflect either genuine white space or simply that the branch is still emerging.
Citation counts are sharply front-loaded: the top-cited record has 115 citations, more than double the fifth-ranked record's 30, and the gap is even larger against the bulk of the dataset. This means a small number of early filings on inner-spacer formation and gate structure design have shaped how later applicants draft their claims. Because citation counts inside a searched corpus favour older records, this concentration should be read as a marker of historical influence on claim language, not as a statement about which patents matter most for a design today.
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Disclaimer. This page is generated from Patsnap Eureka data drawn from a limited snapshot of global patent and scientific-literature records, and is provided for general information and reference only.
Patent data carries inherent limitations: recent filings (typically the most recent 18–24 months) are under-counted due to standard publication lag; counts may be reported at either a patent-family or a patent-record basis and are not always directly comparable; classification, applicant-name, and citation data may contain errors, duplicates, or omissions; and the underlying search query defines and constrains the scope shown. As a result, the analysis may be incomplete or inaccurate and may not reflect the full technology landscape.
Nothing on this page constitutes an exhaustive prior-art, novelty, freedom-to-operate, or validity search, nor does it constitute legal, financial, investment, or professional advice, and it should not be relied upon as such. Any patent, commercial, or strategic decision should be verified independently and reviewed with qualified patent, legal, and domain professionals. Patsnap makes no warranties, express or implied, as to the accuracy, completeness, or fitness for any particular purpose of the information presented.
Machine translation. Assignee and organisation names originally recorded in Chinese, Japanese or Korean have been rendered into English by an AI translation step so that the tables stay readable. These renderings are best-effort and may not match a company’s registered English name; the original name is what the underlying patent record carries, and it is what any Eureka query launched from this page uses.