Nanosheet Transistor Doping and Implantation Patent Landscape 2026
- Filing activity peaked in 2019 at 77 and has since declined, with the 2022 midpoint at 62 — the claim space around doping and implantation for gate-all-around structures is no longer expanding.
- 477 of the tracked filings route through the United States receiving office, against single digits for China, India and South Korea — this is a US-prosecution-first field.
- Recent-year momentum has nearly stopped even among the largest holders, with IBM logging just 1 filing in the latest year and the rest of the top group at 0.
Filing growth compares 2021 (75 records) with 2024 (59) — a three-year span. 2024 is the most recent year we treat as complete: publication lags filing by roughly 18 months, so 2025 onwards are still filling in and any growth rate that ends there would understate the field. Top-5 share is the combined record count of the five largest assignees divided by all 551 records in scope (CR5), not by the ranked leaders only.
What this landscape covers
Gate-all-around and nanosheet FET architectures replace the planar or FinFET channel with stacked, fully wrapped sheets, and doping those sheets uniformly is one of the harder integration problems in the transition. This landscape isolates patent activity at the intersection of nanosheet/gate-all-around device claims and ion implantation, conformal doping, dopant activation and doping-process claims, using IPC classes tied to implantation and junction formation (H01L21/265, H01L29/423, H01L21/336). The dataset spans 551 published records treated as patent families.
Publication lags filing by roughly 18 months, so the last one to two years in any trend chart will always look thinner than the true filing rate once later publications catch up.
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Filing trend and technology composition
The trend line and the IPC spread below both point to a field that built up its claim base early and is now consolidating rather than expanding into new subclasses.
Filings rose then fell
Filings climbed from 36 in 2017 to a peak of 77 in 2019, held near that level through the 2022 midpoint of 62, and have tapered since — the partial 2026 count of 2 reflects publication lag rather than a sudden stop.
Concentrated in core semiconductor-device classes
Every record sits under H01L, and the bulk of secondary classification lands in H10D (233) and H10P (60), the general semiconductor-device buckets. Memory-device manufacture (H10B, 43) and nanotechnology applications (B82Y, 39) are present but secondary, and electron-tube and crystal-growth classes (H01J, C30B) appear only as edge cases — this is squarely a logic/transistor-integration story, not a memory or materials-growth one.
Shares are the percentage of the 551 records in scope. A patent can carry several IPC classes, so the shares add up to more than 100%.
Go deeper on Nanosheet Transistor Doping and Implantation with Eureka
This page is one run against one query. Ask Eureka your own question about nanosheet transistor doping and implantation and every answer comes back with the patent numbers behind it.
Try EurekaThe records other filings build on
Formation of self-limited inner spacer for gate-all-around nanosheet fet
A semiconductor structure containing a gate-all-around nanosheet field effect transistor having a self-limited inner spacer composed of a rare earth doped germanium dioxide that provides source/drain isolation between rare earth metal silicide ohmic contacts is provided.Filed by International Business Machines Corporation; published as US20190393306A1.
| # | Publication no. | Patent title | Citations |
|---|---|---|---|
| 1 | US20200044087A1 | Sub-fin isolation schemes for gate-all-around transistor devices | 141 |
| 2 | US9786774B2 | Metal gate of gate-all-around transistor | 141 |
| 3 | US9520466B2 | Vertical gate-all-around field effect transistors and methods of forming same | 139 |
| 4 | US20200266060A1 | Gate-all-around field-effect transistor devices having source/drain extension contacts to channel layers for … | 136 |
| 5 | US6495403B1 | Gate-all-around semiconductor device and process for fabricating the same | 130 |
| 6 | US5580802A | Silicon-on-insulator gate-all-around mosfet fabrication methods | 121 |
| 7 | US20190181224A1 | Formation of self-limited inner spacer for gate-all-around nanosheet fet | 115 |
| 8 | US20160027870A1 | Fabrication of perfectly symmetric gate-all-around FET on suspended nanowire using interface interaction | 105 |
| 9 | US20190081155A1 | Nanosheet transistor with improved inner spacer | 103 |
| 10 | US20190131396A1 | Vertically stacked nfets and pfets with gate-all-around structure | 94 |
Citation counts inside a searched corpus favour older, earlier-published records — read this as a map of foundational architecture claims (sub-fin isolation, metal gate, vertical GAA structure, source/drain extension contacts), not as a ranking of current relevance.
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Browse MCP servers →What the numbers mean for a filing decision
Three signals matter most for anyone deciding where to put a new claim in this space: where the filings actually publish, how citation weight distributes, and how flat recent momentum has become.
This is a US-first prosecution field
With WIPO, Europe, China, India and South Korea each in the single or low double digits, the working assumption for freedom-to-operate is that the binding prior art will be found in US filings, not in a scattered global set.
Growth has already peaked
The filing curve rose fast to 2019 and has been flat-to-declining since, including at the 2022 midpoint. High density earlier in the window means claim space around core doping and implantation methods is occupied, not that the underlying technology is finished evolving.
Co-filing is rare and mostly intra-company
Only 10 co-assignee pairs appear across 551 families, and the strongest links are university-industry (TSMC with National Taiwan University) or intra-corporate (IBM with its UK IP unit, IBM with IBM China) rather than cross-competitor alliances.
Eureka can read the same corpus for gaps instead of for coverage: under-claimed branches adjacent to nanosheet transistor doping and implantation, with the prior art for and against each one.
| Assignee | Co-assignee | Shared families |
|---|---|---|
| Taiwan Semiconductor Manufacturing Company (TSMC) | National Taiwan University | 5 |
| International Business Machines Corporation (IBM) | IBM UNITED KINGDOM LTD INTELLECTUAL PROPERTY DEPARTMENT | 4 |
| International Business Machines Corporation (IBM) | IBM (China) Co., Ltd. | 2 |
| International Business Machines Corporation (IBM) | IBM DEUTSCHLAND GMBH | 2 |
| Korea Advanced Institute of Science and Technology (KAIST) | Integrated Smart Sensors Center Foundation | 2 |
| Interuniversity Microelectronics Centre (IMEC) | Katholieke Universiteit Leuven (KU Leuven) | 2 |
| Intel Corporation | RACHMADY WILLY | 1 |
| Intel Corporation | MURTHY ANAND S | 1 |
The strongest co-assignee pairing in the dataset links Taiwan Semiconductor Manufacturing Company (TSMC) (TSMC) with National Taiwan University at 5 shared families — a pattern of academic co-invention rather than industry consortium filing.
Who holds the ground, and where it is thin
Recent-year momentum has slowed across the board, which changes how to read the assignee ranking: a large historical family count no longer implies active current filing.
IBM is the only top holder still filing
International Business Machines Corporation (IBM) (IBM) logged 1 filing in the latest tracked year while every other major holder in the recent-momentum set — TSMC, Applied Materials, Intel, STMicroelectronics and Samsung — logged 0.
The densest single collaboration in the set
Taiwan Semiconductor Manufacturing Company (TSMC) and National Taiwan University co-assign more families together than any other pair tracked, pointing to a standing research relationship rather than one-off co-invention.
A large but now-settling corpus
The ranking draws on all 551 families in the dataset; concentration at the top of that ranking sits alongside a long tail of single-filing entrants who appear once and do not return.
| Assignee | Recent year | YoY |
|---|---|---|
| International Business Machines Corporation (IBM) | 1 | — |
| Taiwan Semiconductor Manufacturing Company (TSMC) | 0 | — |
| Applied Materials, Inc. | 0 | — |
| Intel Corporation | 0 | — |
| STMICROELECTRONICS INC | 0 | — |
| Samsung Electronics Co., Ltd. (South Korea) | 0 | — |
| Qualcomm Incorporated | 0 | -100% |
| Korea Advanced Institute of Science and Technology (KAIST) | 0 | — |
Where to take this
The dataset points to two practical next steps: confirm freedom-to-operate against the densest foundational claims, and pressure-test any new filing idea against the under-claimed sub-areas rather than the crowded core.
Run a freedom-to-operate check on the foundational claims
Sub-fin isolation, metal gate structure and vertical GAA architecture carry the heaviest citation weight in this set. A new doping or implantation claim that touches these structural elements needs to be checked against them specifically, not against the corpus average.
Check claims in Eureka →Draft against the under-claimed sub-areas
Sequencing of dopant activation anneals across stacked sheets and conformal doping uniformity at variable sheet spacing both sit outside the densest citation clusters. Drafting a first claim there starts from open ground rather than around existing blocking art.
Explore white space in Eureka →Common questions on this landscape
A record qualifies if it combines nanosheet, gate-all-around, or nanosheet FET terminology in the title or abstract with implantation- or doping-related terms such as ion implantation, conformal doping, dopant activation, or doping process in the title, claims, or description. It must also carry an IPC classification tied to junction formation or field-effect device structure (H01L21/265, H01L29/423, or H01L21/336). This combination isolates doping and implantation methods specific to stacked-channel architectures rather than general GAA structural claims.
Filings rose from 36 in 2017 to a peak of 77 in 2019, then held near 62 by the 2022 midpoint before tapering. This pattern is consistent with early, dense staking of core doping and implantation methods as GAA architectures moved toward production, followed by a shift toward refinement claims once the foundational ground was occupied. The most recent one to two years will always look artificially low because publication lags filing by roughly 18 months, so the true 2025-2026 filing rate is understated in any chart drawn from publication dates.
Among the largest historical holders tracked for recent-year momentum, only International Business Machines Corporation (IBM) (IBM) shows any activity in the latest year, with 1 filing. TSMC, Applied Materials, Intel, STMicroelectronics and Samsung all show 0 filings in that same window. A large historical family count does not mean a company is still actively claiming new ground here — check recent-year momentum separately from total family count before assuming a competitor is active.
The densest citation clusters sit around structural elements — sub-fin isolation, metal gate formation, vertical GAA architecture and source/drain extension contacts. Sub-areas adjacent to but distinct from these, such as dopant activation anneal sequencing across stacked sheets, conformal doping uniformity at variable sheet spacing, and implant dose control for asymmetric sheet counts, show less claim density. These are reasonable starting points for a first claim, though a full freedom-to-operate search against the specific structural claims is still necessary before filing.
No. High filing density in H01L21/265, H01L29/423 and H01L21/336 means that claim space around common doping and implantation approaches is occupied, not that the underlying integration challenge is resolved. The flat-to-declining recent trend could reflect either technical maturity or a strategic shift by major holders toward adjacent claim types not captured by this exact search combination. Treat filing volume as a map of where claims already exist, not a verdict on remaining technical difficulty.
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Disclaimer. This page is generated from Patsnap Eureka data drawn from a limited snapshot of global patent and scientific-literature records, and is provided for general information and reference only.
Patent data carries inherent limitations: recent filings (typically the most recent 18–24 months) are under-counted due to standard publication lag; counts may be reported at either a patent-family or a patent-record basis and are not always directly comparable; classification, applicant-name, and citation data may contain errors, duplicates, or omissions; and the underlying search query defines and constrains the scope shown. As a result, the analysis may be incomplete or inaccurate and may not reflect the full technology landscape.
Nothing on this page constitutes an exhaustive prior-art, novelty, freedom-to-operate, or validity search, nor does it constitute legal, financial, investment, or professional advice, and it should not be relied upon as such. Any patent, commercial, or strategic decision should be verified independently and reviewed with qualified patent, legal, and domain professionals. Patsnap makes no warranties, express or implied, as to the accuracy, completeness, or fitness for any particular purpose of the information presented.
Machine translation. Assignee and organisation names originally recorded in Chinese, Japanese or Korean have been rendered into English by an AI translation step so that the tables stay readable. These renderings are best-effort and may not match a company’s registered English name; the original name is what the underlying patent record carries, and it is what any Eureka query launched from this page uses.