Nanosheet Transistor Patents: Who Leads, Where the Gaps Are 2026
- Filing peaked in 2023 at 13 families, then softened toward the 2026 partial year — the field has stopped accelerating even before publication lag is accounted for.
- No single assignee dominates recent-year momentum; the largest latest-year filer logged only 2 families, with several individual inventors matching that pace.
- United States filings outnumber the next four receiving offices combined, with WIPO PCT and India as the clearest secondary filing routes.
Filing growth compares 2021 (4 records) with 2024 (12) — a three-year span. 2024 is the most recent year we treat as complete: publication lags filing by roughly 18 months, so 2025 onwards are still filling in and any growth rate that ends there would understate the field.
What this landscape covers
This dataset tracks 47 patent families filed between 2015 and mid-2026 that combine nanosheet, gate-all-around and nanosheet FET terminology with claims specifically addressing device scaling, gate pitch scaling, 3D stacking or area reduction. The IPC scope is narrowed to H01L29/775, H01L21/8238 and H01L27/06 — the classification families most closely tied to gate-all-around device structure and fabrication rather than generic transistor art.
Filing activity is concentrated in the years following 2020, peaking in 2023 before slowing. Because publication typically lags filing by around 18 months, the 2025-2026 counts in this dataset are undercounts of actual filing activity, not necessarily a real slowdown.
Filing trend and technology composition
Two views of the same 47-family dataset: how filing volume has moved year over year, and how those families distribute across IPC subclasses.
Filing trend: rise, peak, plateau
Filings moved from zero in 2017 to a peak of 13 in 2023, with the 2022 midpoint at 6 — a doubling in a single year followed by a flattening rather than sustained growth. The 2026 figure of 3 is a partial-year count and should not be read as a decline yet.
IPC composition: concentrated but not singular
H01L carries all 47 records by definition of the search scope, but H10D — the newer semiconductor-devices general classification — already overlaps 23 of them, showing active reclassification of gate-all-around art. B82Y and H10W each cover only 4 records, and H10B/G11C barely register, indicating that memory-integration angles on nanosheet transistors remain a minor share of filings so far.
Shares are the percentage of the 47 records in scope. A patent can carry several IPC classes, so the shares add up to more than 100%.
Go deeper on Nanosheet Transistor Miniaturization and Integration with Eureka
This page is one run against one query. Ask Eureka your own question about nanosheet transistor miniaturization and integration and every answer comes back with the patent numbers behind it.
Try EurekaThe most-cited records in this dataset
Forming n-type and p-type horizontal gate-all-around devices
An approach provides a semiconductor structure for a first device with a first plurality of channels with a larger horizontal dimension than a vertical dimension of the first plurality of channels a second device comprising a second plurality of channels with a smaller horizontal dimension than the vertical dimension of the second plurality of channels. The first plurality of channels and the second plurality of channels have a same channel width in embodiments of the present invention. The first device is an n-type horizontal gate-all-around device and the second device is a p-type horizontal gate-all-around device.Filed by International Business Machines Corporation, published 2023-03-16 as US20230079751A1.
| # | Publication no. | Patent title | Citations |
|---|---|---|---|
| 1 | US20200373300A1 | Multi-threshold voltage gate-all-around transistors | 74 |
| 2 | US10734286B1 | Multiple dielectrics for gate-all-around transistors | 34 |
| 3 | US20200388681A1 | Channel orientation of CMOS gate-all-around field-effect transistor devices for enhanced carrier mobility | 24 |
| 4 | US20210119021A1 | Methods for GAA I/O formation by selective epi regrowth | 22 |
| 5 | US10892331B2 | Channel orientation of CMOS gate-all-around field-effect transistor devices for enhanced carrier mobility | 10 |
| 6 | US11133309B2 | Multi-threshold voltage gate-all-around transistors | 6 |
| 7 | US20240204109A1 | Complementary field effect transistor (CFET) with balanced n and p drive current | 4 |
| 8 | US20240332388A1 | Methods of reducing backside contact resistance | 3 |
| 9 | WO2024137197A1 | Complementary field effect transistor (CFET) with balanced n and p drive current | 3 |
| 10 | US20240055429A1 | 2d-material gate-all-around complementary FET integration | 3 |
Ranked by citation count within this corpus. Older records accumulate citations simply by being available longer, so treat this as a map of influence, not of current filing priority.
Each row carries its publication number; clicking a row searches Eureka by that number.
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Browse MCP servers →What the numbers mean for filing strategy
Read together, the trend, the citation table and the classification split point to a field where core structural claims were staked early and later filers are working narrower, more specific angles.
Growth has plateaued, not accelerated
The jump from 6 filings at the 2022 midpoint to 13 in 2023 looks like an inflection, but the following years do not extend it. Treat 2023 as the high-water mark to date rather than the start of a trend.
Influence sits with a small handful of early filings
The most-cited record carries more than double the citations of the next entry, and the top five span structural claims on multi-threshold voltage, dielectric stacking and channel orientation. These are the claims a freedom-to-operate search should check first.
Reclassification signals a maturing structure class
Nearly half of the dataset's records also sit in H10D, the newer general semiconductor-device classification, ahead of B82Y nanotechnology and H10W. Memory-integration classes (H10B, G11C) are barely present, suggesting logic-side scaling claims are filed well ahead of memory-integration claims.
US-first filing with a thin international tail
United States filings outweigh the next four offices combined. WIPO PCT and India form the clearest secondary route, while Philippines and EPO filings are each in single digits — international coverage here is still selective rather than routine.
Eureka can read the same corpus for gaps instead of for coverage: under-claimed branches adjacent to nanosheet transistor miniaturization and integration, with the prior art for and against each one.
Who is filing, and how concentrated is it
No assignee in this dataset shows heavy latest-year volume. Momentum is split between one corporate filer and a cluster of individually named co-inventors, with legacy corporate filers showing zero latest-year activity.
Qualcomm Incorporated (Qualcomm)
The only assignee to clear more than one filing in the latest year tracked, though at a modest absolute pace that does not suggest a filing surge.
VISHWAS ACHARYA and co-inventors
A group of individually named inventors — including HIMANSHU MAROTHYA, GAGAN and DEVENDER KUMAR SONI — appear as recurring co-assignee pairs, each contributing one family in the latest year.
International Business Machines Corporation (IBM) (IBM)
IBM holds the representative structural record in this dataset but shows no latest-year filing activity, consistent with earlier-staked structural claims rather than an ongoing filing campaign.
| Assignee | Recent year | YoY |
|---|---|---|
| Qualcomm Incorporated | 2 | — |
| VISHWAS ACHARYA | 1 | — |
| HIMANSHU MAROTHYA | 1 | — |
| GAGAN | 1 | — |
| DEVENDER KUMAR SONI | 1 | — |
| International Business Machines Corporation (IBM) | 0 | — |
| Applied Materials, Inc. | 0 | — |
| Taiwan Semiconductor Manufacturing Company, Ltd. (TSMC) | 0 | — |
Where to take this analysis
The dataset points to a field with staked structural claims and a thin, fragmented tail of recent filers. Two directions follow from that.
Check freedom-to-operate against the top-cited records
The five most-cited records concentrate on multi-threshold voltage control, dielectric stacking and channel orientation. Any new filing on these mechanisms should be benchmarked against them first.
Explore in Eureka →Watch the under-claimed branches for early movers
Memory-integrated nanosheet stacking and selective epi regrowth for I/O formation show thin filing density relative to the core structural claims — early filers there face less crowded prior art.
Explore in Eureka →Common questions about nanosheet transistor patents
Within this dataset of 47 patent families, no single assignee holds a dominant share. International Business Machines Corporation holds the representative structural record on n-type and p-type horizontal gate-all-around devices, but shows no filings in the latest year tracked. The most recent-year filing activity instead comes from Qualcomm at a modest pace, alongside a cluster of individually named co-inventors filing one family each. This spread suggests the field has moved past its initial structural land-grab into narrower, more distributed filing.
In patent search terms, gate-all-around (GAA) is the broader structural category describing any transistor where the gate wraps fully around the channel, while nanosheet FET refers to a specific channel geometry within that category using wide, sheet-like channels rather than nanowires. This dataset's search string treats them as overlapping terms because most recent filings use both interchangeably in claims and titles. Practically, a nanosheet FET claim is a species claim inside the GAA genus, so a freedom-to-operate check on nanosheet structures should also cover general GAA prior art.
Filings in this dataset rose from zero in 2017 to a peak of 13 in 2023, roughly doubling from the 6-filing midpoint recorded in 2022. This pattern is consistent with the semiconductor industry's public roadmap shift toward gate-all-around structures for sub-3nm logic nodes around that period, which drove concentrated filing on scaling and integration claims. The apparent slowdown after 2023 should be read cautiously, however, since publication typically lags actual filing by around 18 months, meaning 2025 and 2026 counts are still incomplete.
The classification data shows thin coverage in memory-integration classes such as H10B and G11C, which together account for only 3 of the 47 records, compared to the dense overlap between H01L and H10D. This suggests that while logic-side scaling and gate structure claims are well staked, claims combining nanosheet transistor structures with memory-array integration are comparatively open. Selective epitaxial regrowth for I/O formation and N/P device channel-width matching also show fewer citing records relative to the core structural patents, indicating room for narrower claims in those areas.
The United States is the leading receiving office in this dataset with 28 filings, more than the next four offices combined. WIPO's PCT route accounts for 8 filings, making it the clearest path for filers seeking international coverage, followed by India at 6. The Philippines and the European Patent Office each register only a handful of filings, indicating that international coverage beyond the US and PCT route remains selective rather than standard practice for this technology.
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Disclaimer. This page is generated from Patsnap Eureka data drawn from a limited snapshot of global patent and scientific-literature records, and is provided for general information and reference only.
Patent data carries inherent limitations: recent filings (typically the most recent 18–24 months) are under-counted due to standard publication lag; counts may be reported at either a patent-family or a patent-record basis and are not always directly comparable; classification, applicant-name, and citation data may contain errors, duplicates, or omissions; and the underlying search query defines and constrains the scope shown. As a result, the analysis may be incomplete or inaccurate and may not reflect the full technology landscape.
Nothing on this page constitutes an exhaustive prior-art, novelty, freedom-to-operate, or validity search, nor does it constitute legal, financial, investment, or professional advice, and it should not be relied upon as such. Any patent, commercial, or strategic decision should be verified independently and reviewed with qualified patent, legal, and domain professionals. Patsnap makes no warranties, express or implied, as to the accuracy, completeness, or fitness for any particular purpose of the information presented.
Machine translation. Assignee and organisation names originally recorded in Chinese, Japanese or Korean have been rendered into English by an AI translation step so that the tables stay readable. These renderings are best-effort and may not match a company’s registered English name; the original name is what the underlying patent record carries, and it is what any Eureka query launched from this page uses.