A nanosheet transistor is a type of gate-all-around (GAA) field-effect transistor where the channel is formed from one or more stacked, horizontally oriented sheets of semiconductor material, fully surrounded by the gate on all sides. This differs from FinFET, where the gate only wraps three sides of a vertical fin-shaped channel. The full gate wrap in nanosheet devices gives tighter electrostatic control at smaller dimensions, which is why it is the structure most manufacturers cite for continuing to scale logic transistors past the FinFET node.

In this dataset, filings peaked in 2019 at 4 and the 2022 midpoint is also 4, showing no clear upward trend through the tracked window. Part of this is a real signal — foundational structural claims were filed early and the field has moved toward narrower process-integration refinements rather than new base architectures. Part of it is a data artefact: publication typically lags filing by about 18 months, so the most recent one or two years in any patent trend will always look under-filled until later publications catch up.

The most-cited records in this corpus are held by large semiconductor manufacturers and IP holders including International Business Machines Corporation, alongside a set of individually named recent filers with single filings each. Co-assignee data shows only 10 collaborative pairs across the corpus, and the strongest pairs involve one core company plus its own IP department or individual named inventors, rather than cross-company joint filings. That pattern suggests most substantive process-integration IP here is developed and held internally rather than through joint ventures.

US20230170352A1, assigned to International Business Machines Corporation, covers a specific structure: vertically stacked nanosheet nFET and pFET transistors on a self-aligned hybrid substrate, where the two device tiers use channel materials with different crystalline orientations, aimed at 3D area scaling. It does not block nanosheet transistors generally, nor planar or single-tier gate-all-around structures. Anyone building 3D vertical nFET-over-pFET stacks using a self-aligned hybrid substrate with differing channel orientations should review this claim closely; other stacking or alignment methods sit outside its specific combination.

The coating and surface-deposition category (IPC C23C) has only one supporting record against 21 total in this corpus, making deposition chemistry tied specifically to channel release or spacer formation a thin, largely open area. Nanotechnology-application framing (B82Y) is similarly light at three records, suggesting claims that tie nanosheet structure explicitly to nanoscale material-property outcomes are under-argued relative to pure structural claims. Geographically, filings routed first through India-based receiving offices are represented by a single record, which is worth noting for filers weighing where to establish early priority.