Gate-all-around (GAA) describes the broader structural principle of a gate wrapping fully around the channel on all sides, while nanosheet transistors are the specific implementation that stacks multiple thin horizontal channel sheets within a GAA gate. In patent terms, GAA claims tend to be broader structural claims, while nanosheet claims narrow to the stacking geometry, sheet count, sheet thickness or spacing. This corpus deliberately combines both search terms because most recent filings claim the nanosheet implementation of a GAA structure rather than GAA in isolation. Forksheet and CFET (complementary FET) architectures are further specific variants that show up as a smaller, more recent slice of the same combined space.

Influence in this dataset is measured by citation count within the searched corpus, and the most-cited records include foundational structural patents on gate-all-around fabrication and aligned GAA structures dating from earlier in the field's history. Citation counts favour older filings simply because they have had more time to be cited, so a highly-cited record is a signal of foundational influence, not necessarily of current commercial relevance. Cross-referencing the most-cited list against the assignee ranking gives a fuller picture of which companies built the base layer of prior art that later filers had to design around. For an up-to-date competitive view, the recent-year filing momentum matters more than historical citation counts.

The filing trend in this corpus shows a peak of 337 filings in 2022 followed by a decline through the most recent years, which most plausibly reflects the claim space around the core GAA/nanosheet structure becoming crowded — the foundational architecture patents were largely filed in the years leading up to and through the industry's transition from FinFET, and later filers increasingly had to file narrower variants or manufacturing refinements. It is also worth discounting the very latest one to two years, since patent publication lags filing by roughly 18 months and those counts will rise as pending applications publish. Even with that correction, the drop-off from the 2022 peak is large enough that it likely represents a genuine slowdown in new structural filings rather than a reporting artefact alone.

The United States is by far the largest receiving office in this corpus, with 1,526 filings compared to 202 in China, 138 at the EPO, 130 in Taiwan, 119 via the WIPO PCT route and 114 in South Korea. That concentration reflects where advanced-node semiconductor manufacturing and its associated R&D investment are heaviest, and it means most of the enforceable prior art and prosecution history a competitor needs to clear sits in US filings. Companies planning a global filing strategy in this space should still expect meaningful competitive activity in China and Taiwan given their foundry presence, even though the raw filing counts there are smaller.

The clearest under-claimed pockets in this corpus sit at the intersection of nanosheet structures with adjacent process techniques: forksheet dielectric wall isolation, CFET source/drain merge schemes, air-spacer inner spacer formation, and the crossover between nanosheet channel stacking and memory-cell integration reflected in the H10B subclass. These areas show up as smaller counts relative to the dense core H01L/H10D structural claims, which is a sign of open claim space rather than a judgement on technical difficulty. A first claim in these areas would typically need to specify a concrete process or geometric detail — such as a particular spacer material sequence or a specific merge geometry for CFET source/drain regions — to sit clear of the crowded core structural claims.