Synthetic-shift global alignment provides the most rigorous in-die overlay error measurement for multi-patterning processes. The design for the first patterning step is used as a global reference, and the designs for all remaining steps are synthetically shifted until each achieves the best global alignment with the full-wafer image. The final synthetic shift for each step, measured relative to the first patterning step, yields a quantitative map of relative overlay error between any two features printed using multi-patterning technology. Conventional methods relying on special overlay targets placed in die-edge scribe lines do not reliably predict actual in-die overlay, a deficiency that becomes fatal at advanced DRAM pitches where in-die overlay budgets are sub-nanometer.

TSMC's frequency-picked DBO methodology uses a specially designed target architecture comprising a lower-layer pattern with interleaved sub-patterns of two different pitches and an upper-layer pattern at the first pitch. Because the second sub-patterns are arranged at a smaller pitch and interleaved between the first sub-patterns, a frequency discrimination mechanism is created: the overlay error signal is encoded in a specific spatial frequency component of the diffracted spectrum, allowing measurement to be extracted with high selectivity and reduced noise.

For applications where optical diffraction is insufficient—for instance, in buried or fully opaque layer stacks relevant to 3D DRAM structures—atomic force microscopy (AFM) provides a non-optical path. TNO's method describes scanning a probe tip across a multi-layer semiconductor surface while applying an acoustic input signal at a defined first frequency. The probe response is analyzed to extract overlay information between a first and second patterned layer buried in the stack, addressing overlay between device layers not accessible to conventional optical overlay tools.

TSMC's mask-shift-aware RC extraction defines the maximum mask shift as the maximum expected registration error across all manufacturing conditions. For each decomposition of a layout into a first and second mask, the worst-case electrical performance—expressed as capacitance using high-order or piecewise equations—is simulated over the full range of mask shifts bounded by this maximum. This methodology ensures that timing and signal integrity budgets in DRAM peripheral circuits account for the actual distribution of overlay-induced geometric variation, not merely nominal dimensions.

IBM's beat-signal overlay amplification structure exploits the moiré beat phenomenon between two interleaved arrays of different periodicities. The difference in periodicity produces a beat signal whose zero-crossing location is proportional to overlay error, amplified by a proportionality constant much greater than one. This amplification enables conventional optical microscopy to resolve overlay errors that would otherwise be below its detection limit.

IBM's Monte Carlo simulation framework provides a designed circuit structure, samples process variations and positioning deviation errors from statistical distributions, predicts the shape and position of each circuit section on adjacent layers, and compares the superposed dimensions against theoretical minimum values to identify predicted failure modes. For DRAM, where storage capacitor contact-to-active overlay budgets shrink with each node, this statistical forward simulation identifies the most vulnerable feature combinations early in process development.