Overlay Metrology & EPE Patents: Who Leads, Where the Gaps Are 2026
Overlay Metrology and Edge Placement Error Patents
92.9% concentration. The top five assignees together hold 2,643 of the 2,845 records in scope — a field where five companies have effectively closed the door on new entrants. Filings peaked at 285 in 2018 and ran near that level through the early 2020s before falling from 227 in 2021 to 102 in 2024, a -55% move over that three-year span. 2025 and 2026 figures are still incomplete because publication typically lags filing by around 18 months, so the apparent decline in the newest years should not be read as the field slowing.
- 1ASML NETHERLANDS BV1,612
- 2KLA CORP805
- 3KLA TENCOR TECHNOLOGY CORP163
- 4INTERNATIONAL BUSINESS MACHINE CORPORATION34
- 5TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD29
See the full overlay metrology and edge placement error analysis in Eureka
- The complete ranking, not just the top five
- Every IPC branch with its share of the corpus
- The most-cited records, and where claim space is still thin
Common questions about this landscape
Who holds the most overlay metrology patents?
The dataset shows one assignee far ahead of the rest, holding 1,612 of the 2,845 records in scope — more than half the entire field by record count. The next four largest holders combined bring the top five to 2,643 records, or 92.9% of all records in scope. Past that top tier, holdings drop sharply: fifth place holds 29 records and tenth place holds 15, even though the full ranking runs to 100 companies.
Is overlay metrology patent filing slowing down?
Filings did fall from 227 in 2021 to 102 in 2024, a -55% change over that span, but this should not be read as the field cooling. Patent publication typically lags filing by around 18 months, so the 2025 and 2026 figures in any dataset cut off in mid-2026 are structurally incomplete. The safer read is that 2024 is the most recent complete year, and it still shows over a hundred filings.
What is edge placement error and why does it show up alongside overlay metrology in patents?
Edge placement error is the cumulative positional deviation of a feature edge relative to its intended location, aggregating overlay error, critical-dimension variation and other process shifts across a multi-patterning stack. It matters more than overlay alone once a design uses several lithography and etch steps to build one layer, because small overlay errors compound. Patent filers treat the two together because a target design or correction scheme aimed at overlay control usually also affects the edge placement error budget downstream.
Disclaimer. This analysis is based on Patsnap Eureka data drawn from a limited snapshot of global patent records and is provided for general information and reference only. Patent data carries inherent limitations — recent filings are under-counted because of publication lag, counts may be on a record or family basis, classification and applicant-name data may contain errors or duplicates, and the underlying search query defines the scope shown — so the analysis may be incomplete or inaccurate and may not reflect the full technology landscape.
Nothing here is an exhaustive prior-art, novelty, freedom-to-operate or validity search, nor does it constitute legal, financial or professional advice, and it should not be relied upon as such. Verify independently and review with qualified patent and legal professionals before acting on it.
Method: Filing trend and technology composition. Derived from a Patsnap search on Overlay Metrology and Edge Placement Error covering 2015–2026, data cut-off 2026-07-31. Counts reflect published records only and shift as new filings publish. Every share divides by all records in scope. Data: Patsnap Eureka. See the full landscape report.