The dataset shows one assignee far ahead of the rest, holding 1,612 of the 2,845 records in scope — more than half the entire field by record count. The next four largest holders combined bring the top five to 2,643 records, or 92.9% of all records in scope. Past that top tier, holdings drop sharply: fifth place holds 29 records and tenth place holds 15, even though the full ranking runs to 100 companies.

Filings did fall from 227 in 2021 to 102 in 2024, a -55% change over that span, but this should not be read as the field cooling. Patent publication typically lags filing by around 18 months, so the 2025 and 2026 figures in any dataset cut off in mid-2026 are structurally incomplete. The safer read is that 2024 is the most recent complete year, and it still shows over a hundred filings.

Edge placement error is the cumulative positional deviation of a feature edge relative to its intended location, aggregating overlay error, critical-dimension variation and other process shifts across a multi-patterning stack. It matters more than overlay alone once a design uses several lithography and etch steps to build one layer, because small overlay errors compound. Patent filers treat the two together because a target design or correction scheme aimed at overlay control usually also affects the edge placement error budget downstream.

The technology composition data shows heavy concentration in G03F photolithography classification, at 76.1% of the 2,845 records, with lighter coverage in adjacent branches like machine-learning-driven grating asymmetry correction and in-die sampling plan optimisation. These branches sit in the same functional area but have not accumulated the same claim density, meaning a well-drafted filing there is less likely to read directly onto existing dominant portfolios. Any freedom-to-operate check should still start with the leading assignee's holdings before relying on white space alone.

At 92.9% of all 2,845 records held by the top five assignees, this field is unusually concentrated even by semiconductor-equipment standards, where a handful of tool makers and foundries typically dominate. The concentration is driven by the capital and metrology-hardware intensity of the technology: building and validating an overlay measurement tool requires equipment infrastructure that only a few companies have, which limits the pool of realistic filers. That structure makes the leader's portfolio the practical starting point for any competitive or freedom-to-operate analysis in this space.