Panel Level Packaging Substrates Patents: Top Companies & Trends 2026
- 47.4% concentration. The top 5 of 41 ranked assignees hold 81 of 171 records in scope — just under half the field sits with a handful of filers.
- Growth cooled after 2021. Filings peaked at 20 in 2021 and fell to 12 by 2024, a 40% decline over that three-year span.
- One subclass dominates. H01L covers 94.2% of records, while adjacent branches like B81B (MEMS) and H05K (printed circuits) sit under 5% each — a sign of where claim space is still thin.
Filing growth compares 2021 (20 records) with 2024 (12) — a three-year span. 2024 is the most recent year we treat as complete: publication lags filing by roughly 18 months, so 2025 onwards are still filling in and any growth rate that ends there would understate the field. Top-5 share is the combined record count of the five largest assignees divided by all 171 records in scope (CR5), not by the ranked leaders only.
What the panel level packaging substrate patent record shows
Panel level packaging (PLP) substrates address a structural problem in semiconductor packaging: how to process many die on a large-format panel rather than a round wafer, without losing die alignment or fighting warpage during mold compound cure and singulation. The 171 records in scope span die-shift correction, stepper field stitching, thin-panel handling and singulation methods, spanning 2015 through the 2026 cut-off. Filing activity is concentrated in a narrow band of assignees, with the top 5 of 41 ranked companies accounting for 47.4% of all records, and the top 10 reaching 70.2% — a field where a small number of players have staked out most of the claim territory.
Filing rose steadily through the late 2010s, peaked in 2021, and has since pulled back. Because publication lags filing by roughly 18 months, the last one to two years understate true filing activity and should not be read as a slowdown in interest so much as a gap in visible data.
Filing trend and technology composition
Two views of the same 171-record dataset: how filing volume has moved year over year, and which IPC subclasses the claims fall under.
Filing trend: a 2021 peak, then a pullback
Annual filings rose from 11 in 2017 to a peak of 20 in 2021, then declined to 12 by 2024 — a 40% drop over that three-year span. 2025 and 2026 figures are still filling in due to publication lag and should not be read as a real decline yet.
IPC composition: H01L dominates, adjacent classes are thin
H01L (semiconductor devices) appears in 94.2% of records and H10W in 57.3%, confirming this is fundamentally a semiconductor-device packaging art. Smaller classes — H10B, B41J, C03C, H05K and B81B — each sit at 5.8% or below, marking branches with comparatively little claim density relative to the core.
Shares are the percentage of the 171 records in scope. A patent can carry several IPC classes, so the shares add up to more than 100%.
Go deeper on Panel Level Packaging Substrates with Eureka
This page is one run against one query. Ask Eureka your own question about panel level packaging substrates and every answer comes back with the patent numbers behind it.
Try EurekaThe most-cited prior art and a representative filing
US20200312780A1 — Panel level packaging for devices
Panel level packaging (PLP) with high accuracy and high scalability is disclosed. The PLP employs an alignment carrier with a low coefficient of expansion which is configured with die regions having local die alignment marks. Depending on panel size, it may be segmented into blocks, each with an alignment die region configured for attaching an alignment die, reducing linear and non-linear positional errors.Filed by Pyxis CF Pte. Ltd., published 2020-10-01.
| # | Publication no. | Patent title | Citations |
|---|---|---|---|
| 1 | US20100072588A1 | Substrate structure with die embedded inside and dual build-up layers over both side surfaces and method of t… | 223 |
| 2 | US20100301474A1 | Semiconductor Device Package Structure and Method for the Same | 159 |
| 3 | US20170077022A1 | Fully molded miniaturized semiconductor module | 125 |
| 4 | US20130168849A1 | Fully Molded Fan-Out | 90 |
| 5 | US20160005628A1 | Wafer level packaging method and integrated electronic package | 66 |
| 6 | US20100078655A1 | Substrate structure with die embedded inside and dual build-up layers over both side surfaces and method of t… | 61 |
| 7 | US20210375829A1 | 3D semiconductor device and structure | 58 |
| 8 | WO2019023213A1 | Precision structured glass articles, integrated circuit packages, optical devices, microfluidic devices, and … | 50 |
| 9 | US8237257B2 | Substrate structure with die embedded inside and dual build-up layers over both side surfaces and method of t… | 49 |
| 10 | US9396999B2 | Wafer level packaging method | 47 |
Citation counts favour older filings simply by virtue of being searchable longer — treat them as a signal of influence within this corpus, not as a ranking of current technical importance.
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Browse MCP servers →What the numbers mean for filing strategy
Three patterns stand out once concentration, growth and technology composition are read together.
A small group holds nearly half the field
With the top 5 of 41 ranked assignees accounting for 81 of 171 records, and the top 10 reaching 70.2%, most of the claim space around die alignment, mold compound handling and singulation is already occupied by a short list of filers. New entrants competing head-on in these core claims face dense prior art from established players.
Growth peaked in 2021 and has since cooled
Annual filings rose to a peak of 20 in 2021 before falling to 12 by 2024. That is a real three-year decline, not a data artefact, though 2025-2026 counts are still incomplete due to the roughly 18-month gap between filing and publication.
The art is overwhelmingly semiconductor-device centric
H01L and H10W together dominate the classification mix, while B81B (MEMS), C03C (glass compositions) and H05K (printed circuit assemblies) each sit at 4.1% or below. These smaller classes point to adjacent integration routes — glass-panel carriers, MEMS-compatible processes — that carry far less claim density than the semiconductor-device core.
Eureka can read the same corpus for gaps instead of for coverage: under-claimed branches adjacent to panel level packaging substrates, with the prior art for and against each one.
| Assignee | Co-assignee | Shared families |
|---|---|---|
| Deca Technologies Inc | SCANLAN CHRISTOPHER | 2 |
| Huawei Digital Power Technology Co., Ltd. | MUNDING ANDREAS | 2 |
| Corning Inc | YOON JUN RO | 1 |
| Corning Inc | MCMAHON HUGH M | 1 |
| Corning Inc | LI AIZE | 1 |
| Corning Inc | KIM JIN SU | 1 |
| Corning Inc | DOHN PAUL BENNETT | 1 |
| Corning Inc | BOEK HEATHER DEBRA | 1 |
Only 8 co-assignee pairs appear across 171 records, and the strongest pairings link a single company to individual named inventors rather than to other corporate assignees — this is a field of largely independent filing, not joint development.
Who is filing, and where the gate to entry sits
The ranking spans 41 companies across 171 records. Momentum has cooled across the board: several of the leading assignees, including the top-ranked and fifth-ranked filers, show no filings in the most recent tracked year — consistent with the broader 2021-to-2024 pullback rather than any single company's retreat.
The top filer holds roughly a seventh of the field
The leading assignee's 25 records sit well ahead of the fifth-placed filer's 11 and the tenth-placed filer's 7, showing a steep drop-off rather than a flat distribution among the top ranks.
Most filers hold small, defensive positions
Beyond the top 10 combined 70.2% share, the remaining assignees in the ranking each hold comparatively few records — typical of a field where large integrators and packaging specialists file defensively around narrow process claims.
Even established filers show zero recent activity
Multiple assignees among the leaders, including two with -100% year-over-year momentum, recorded zero filings in the latest tracked year. Given publication lag, this likely reflects incomplete recent data rather than an actual exit from the space.
| Assignee | Recent year | YoY |
|---|---|---|
| Hewlett Packard Development Company, LP | 0 | — |
| Intel Corp | 0 | — |
| Corning Inc | 0 | — |
| Pyxis CF Pte. Ltd. | 0 | — |
| Deca Technologies USA Inc | 0 | -100% |
| Monolithic 3D Inc | 0 | -100% |
| Deca Technologies Inc | 0 | — |
| Huawei Digital Power Technology Co., Ltd. | 0 | — |
Where to take this analysis
The dataset points to a field with a dense core and thinner edges. These are the natural next steps for a team deciding where to file or where to challenge.
Map the white space branches in detail
Classes like B81B, C03C and H05K show low overlap with the H01L core — worth a targeted claim chart before assuming they are open.
Explore white space in EurekaTrack the leading assignees' recent activity
Several top filers show no recent-year filings; confirming whether this is a publication-lag artefact or a real pullback matters for freedom-to-operate calls.
Monitor assignee activity in EurekaReview the most-cited prior art before filing
The five most-cited records anchor die-embedding, fan-out and wafer-level packaging claims that any new filing in this space will need to design around.
Review cited art in EurekaFrequently asked questions
The assignee ranking covers 41 companies across 171 records in scope, with the leading filer holding 25 records versus 11 for the fifth-placed company and 7 for the tenth. The top 5 combined account for 47.4% of all records, and the top 10 reach 70.2%, so filing activity is concentrated among a relatively small group rather than spread evenly. That said, the ranking includes a long tail of companies with only a handful of filings each, which is typical for a packaging process technology where many integrators file defensively around narrow claims.
Filings rose through the late 2010s and peaked at 20 in 2021, then fell to 12 by 2024 — a 40% decline over that three-year span. This is a genuine slowdown over that period rather than noise. However, because publication typically lags actual filing by around 18 months, the 2025 and 2026 figures in the dataset are still incomplete and should not be read as evidence of further decline until later data catches up.
The overwhelming majority — 94.2% of the 171 records in scope — carry an H01L semiconductor-device classification, with H10W appearing in 57.3%. Smaller but notable classes include H10P, H10B (memory device manufacture), B41J, C03C (glass and enamel compositions), H05K (printed circuits) and B81B (MEMS), each covering between roughly 3.5% and 14% of records. Because a single record can carry multiple IPC classes, these shares add up to more than 100%, and they point to where panel-level packaging intersects with adjacent hardware categories like glass carriers and MEMS integration.
US20200312780A1, filed by Pyxis CF Pte. Ltd. and published 2020-10-01, describes a panel level packaging method using an alignment carrier with a low coefficient of thermal expansion and local die alignment marks per die-attach region, including a panel segmented into blocks with dedicated alignment dies to reduce linear and non-linear positional errors. It matters because die-shift correction during panel-scale processing is one of the core technical problems in this field, and this filing sits alongside other highly cited records addressing similar alignment and warpage issues. Anyone designing a competing die-alignment scheme for large-format panels should review its claim scope directly rather than relying on the abstract alone.
The classification data shows H01L and H10W dominating the field, while B81B (MEMS-compatible processes), C03C (glass-panel carrier compositions) and H05K (printed-circuit-integrated substrates) each cover 4.1% or less of the 171 records in scope. These lower-density branches suggest areas where fewer claims have been staked, particularly around glass or ceramic carrier materials and MEMS-compatible panel handling, though a full freedom-to-operate review would still be needed before filing there.
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Disclaimer. This page is generated from Patsnap Eureka data drawn from a limited snapshot of global patent and scientific-literature records, and is provided for general information and reference only.
Patent data carries inherent limitations: recent filings (typically the most recent 18–24 months) are under-counted due to standard publication lag; counts may be reported at either a patent-family or a patent-record basis and are not always directly comparable; classification, applicant-name, and citation data may contain errors, duplicates, or omissions; and the underlying search query defines and constrains the scope shown. As a result, the analysis may be incomplete or inaccurate and may not reflect the full technology landscape.
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Machine translation. Assignee and organisation names originally recorded in Chinese, Japanese or Korean have been rendered into English by an AI translation step so that the tables stay readable. These renderings are best-effort and may not match a company’s registered English name; the original name is what the underlying patent record carries, and it is what any Eureka query launched from this page uses.