PCIe & High-Speed Interconnect Patents: Leaders & White Space 2026
- Filing has cooled since its 2018 peak. 13 families that year against a flat-to-declining trend through the 2022 midpoint of 5, with the most recent year necessarily undercounted by publication lag.
- Claim density concentrates in one IPC subclass. 247 of 253 families sit in G06F digital data processing, versus 35 in H04L transmission — the interconnect's control logic, not its physical-layer signalling, is where most claims live.
- Co-filing clusters around a small inventor group. Only 10 co-assignee pairs exist across the corpus, and the three strongest all share one inventor, pointing to a tight internal team rather than broad industry collaboration.
Filing growth compares 2021 (3 records) with 2024 (4) — a three-year span. 2024 is the most recent year we treat as complete: publication lags filing by roughly 18 months, so 2025 onwards are still filling in and any growth rate that ends there would understate the field. Top-5 share is the combined record count of the five largest assignees divided by all 253 records in scope (CR5), not by the ranked leaders only.
What this landscape covers
This dataset tracks 253 patent families published between 2015 and mid-2026 that combine PCI Express, PCIe interconnect, or high-speed serial link language in the title or abstract with claim-level detail on link training, signal integrity, lane configuration, equalization, or error correction. The IPC filter narrows further to G06F13 (digital data processing I/O), H04L25 and H04L49 (digital transmission and switching), which is why the composition below skews so heavily toward control and management logic rather than raw physical-layer transceiver design.
Filing activity peaked in 2018 and has not recovered that level since, with the 2022 midpoint sitting at roughly a third of peak volume. That flat-to-declining shape is consistent with a maturing standard where core mechanisms are settled and later filings narrow into implementation variants — a pattern worth checking against the specific claim language before assuming the field is closed.
Let an AI agent run this analysis on your own technology
Pick a task. Every answer cites the patents behind it.
Filing trend and technology composition
Two views of the same 253-family corpus: how filing volume has moved year over year, and how those families distribute across IPC subclasses.
Filing trend, 2017–2026
Volume rose to a peak of 13 families in 2018, fell back toward the 2022 midpoint of 5, and the final years understate true filing activity because publication typically lags filing by around 18 months.
IPC subclass composition
G06F accounts for 247 of 253 records — the overwhelming majority — while H04L (35), H05K (8), H03M (7), H04B (6) and smaller subclasses cover packaging, coding and general transmission aspects that ride alongside the core interconnect claims.
Shares are the percentage of the 253 records in scope. A patent can carry several IPC classes, so the shares add up to more than 100%.
Go deeper on PCIe and High-Speed Interconnect with Eureka
This page is one run against one query. Ask Eureka your own question about pcie and high-speed interconnect and every answer comes back with the patent numbers behind it.
Try EurekaRepresentative filing and most-cited prior art
Configuring PCI express module using hardware in a memory sub-system
A first set of parameter values are programed to a first set of sequencer registers. A second set of parameter values are programmed to a second set of sequencer registers. In response to a detecting a triggering event, a hardware sequencer performs the following operations: transfer the first set of parameter values from the first set of sequencer registers to a first set of link training registers, transfer the second set of parameter values from the second set of sequencer registers to a second set of link training registers, and initiate one end of a communication link training with a host.Filed by Micron Technology and published 2026-07-02, this record sits at the newest edge of the dataset — a hardware sequencer that offloads link-training register programming rather than routing it through firmware, which narrows the design space for anyone building a comparable in-memory PCIe controller.
| # | Publication no. | Patent title | Citations |
|---|---|---|---|
| 1 | US20060242354A1 | Flexible routing and addressing | 188 |
| 2 | US7457897B1 | PCI express-compatible controller and interface for flash memory | 180 |
| 3 | US7293129B2 | Flexible routing and addressing | 114 |
| 4 | US20090006710A1 | Virtualization of a host computer's native I/O system architecture via the internet and LANs | 113 |
| 5 | US8782321B2 | PCI express tunneling over a multi-protocol I/O interconnect | 96 |
| 6 | US20090049222A1 | PCI Express-Compatible Controller And Interface For Flash Memory | 96 |
| 7 | US7734859B2 | Virtualization of a host computer's native I/O system architecture via the internet and LANs | 96 |
| 8 | US20060271713A1 | Computing device with flexibly configurable expansion slots, and method of operation | 96 |
| 9 | US7743197B2 | System and method for virtualizing PCIe devices | 94 |
| 10 | US7257655B1 | Embedded PCI-Express implementation | 90 |
Citation counts favour older filings simply because they have had more time to accumulate citations within the searched corpus — read them as a signal of influence on later work, not as a measure of current relevance.
Each row carries its publication number; clicking a row searches Eureka by that number.
Put your own technology through the same analysis
Eureka on the web
When you want the answer in the next five minutes.
The agent works the prompt against patents and technical literature, citing every source.
Run your analysis now →MCP server & REST API
When it has to run inside your own pipeline.
Patent search, landscape analysis and assignee resolution as MCP tools. Drop them into any agent framework, or call REST directly.
Browse MCP servers →What the numbers say
Three read-throughs from the filing, jurisdiction and citation data that matter for a filing or freedom-to-operate decision.
Volume has not recovered since 2018
The corpus peaks in 2018 at 13 families and sits at 5 by the 2022 midpoint, a flat-to-declining trajectory rather than a growth curve. Treat the final one or two years as undercounted given typical 18-month publication lag.
Filing is heavily US-centric
United States receiving-office filings account for the large majority of the corpus, with EPO, WIPO/PCT and Japan trailing well behind. A freedom-to-operate review focused only on US filings would still miss meaningful EPO and PCT coverage.
Control logic dominates over physical-layer claims
Nearly all records sit in G06F rather than H04L, meaning the claim density in this corpus is concentrated in data-processing and I/O management logic — link training state machines, lane negotiation, error handling — rather than transceiver-level signal design.
Co-filing is narrow and inventor-driven
Only 10 co-assignee pairs appear across 253 families, and the strongest three all involve the same inventor paired with different collaborators. This looks like a small internal team filing serially rather than a broad cross-company research effort.
Eureka can read the same corpus for gaps instead of for coverage: under-claimed branches adjacent to pcie and high-speed interconnect, with the prior art for and against each one.
| Assignee | Co-assignee | Shared families |
|---|---|---|
| AJANOVIC JASMIN | WEISSMANN ELIEZER | 11 |
| AJANOVIC JASMIN | WAGH MAHESH | 11 |
| AJANOVIC JASMIN | VASUDEVAN ANIL | 11 |
| AJANOVIC JASMIN | TAMARI ERAN | 11 |
| AJANOVIC JASMIN | SHAMIA DORON | 11 |
| AJANOVIC JASMIN | SETHI PRASHANT | 11 |
| AJANOVIC JASMIN | RODGERS SCOTT DION | 11 |
| AJANOVIC JASMIN | PARDO ILAN | 11 |
AJANOVIC JASMIN appears in all three of the strongest co-assignee pairings in this corpus, each tied at 11 shared filings — a signature of one prolific inventor anchoring a small internal team rather than cross-company co-development.
Who holds the claim positions
Recent-year momentum across the leading assignees has gone flat: every one of the top names in this corpus shows zero filings in the latest year, consistent with the broader publication-lag effect rather than a sign these players have exited the space.
Intel Corporation (Intel)
Anchors the corpus alongside its named inventors, with the strongest co-assignee pairings in the dataset running through a shared inventor team. Its recent-year filing count reads as zero, which is best read against the corpus-wide publication lag rather than as a pullback.
International Business Machines Corporation (IBM) (IBM)
Appears among the top assignees by family count in this corpus, with its filing footprint concentrated in the same G06F-heavy control-logic space that dominates the dataset overall.
HARRIMAN DAVID J
A named-inventor entry ranking among the corpus's most active filers, reflecting how much of this landscape's ownership sits with individual inventors and small internal teams rather than large distributed R&D groups.
ATI Technologies ULC (ATI Technologies)
Rounds out the top tier of assignees in this corpus, its presence a reminder that graphics and interconnect IP holders overlap in PCIe claim territory even outside pure CPU/chipset vendors.
| Assignee | Recent year | YoY |
|---|---|---|
| Intel Corporation | 0 | — |
| International Business Machines Corporation (IBM) | 0 | — |
| HARRIMAN DAVID J | 0 | — |
| ATI Technologies ULC | 0 | — |
| AJANOVIC JASMIN | 0 | — |
| WEISSMANN ELIEZER | 0 | — |
| WAGH MAHESH | 0 | — |
| VASUDEVAN ANIL | 0 | — |
Where to take this
The filing and citation patterns above point to specific next steps depending on whether the goal is freedom-to-operate, white-space filing, or competitive tracking.
Check claim scope on the newest filings
The 2026 Micron record on hardware-sequencer link training shows the field is still active at the implementation level even as aggregate volume has flattened. Newer filings deserve a full claim read before assuming the space is settled.
Explore in EurekaMap the under-claimed branches against your own roadmap
Sub-areas like retimer-side calibration and multi-protocol tunneling error recovery show thinner claim density than core lane-negotiation logic. That gap is either an opening or a sign the approach has not been commercially proven — worth confirming which.
Explore in EurekaTrack the small inventor clusters, not just company names
Because co-filing here concentrates around a handful of named inventors, monitoring by inventor may surface new filings faster than monitoring by assignee alone.
Explore in EurekaCommon questions about PCIe interconnect patents
This dataset identifies 253 patent families published between 2015 and mid-2026 that combine PCI Express or high-speed serial link terminology with claim-level detail on link training, signal integrity, lane configuration, equalization, or error correction. The figure is drawn from a specific search string and IPC filter (G06F13, H04L25, H04L49), so a broader query on general PCIe technology would return a larger number. Using patent families rather than raw document counts also avoids double-counting continuations and multi-jurisdiction filings of the same invention.
No — filing peaked in 2018 at 13 families in this corpus and has not returned to that level since, with the 2022 midpoint sitting at around 5. That is a flat-to-declining trend rather than a growth curve. The most recent one to two years will always look thinner than they eventually turn out to be, because patent publication typically lags the original filing date by around 18 months.
The corpus's top assignees include Intel, IBM, ATI Technologies, and several named individual inventors, with a cluster of co-filed patents concentrated around one particularly prolific inventor and a small internal team. That pattern — heavy inventor-level concentration rather than broad distributed co-development — suggests the deepest claim positions are held by a small number of long-tenured engineering groups rather than spread evenly across the industry.
Relative to the dense claim territory around core link-training state machines and lane negotiation, sub-areas such as retimer-side signal integrity calibration, thermal-aware lane width renegotiation, and multi-protocol tunneling error recovery show thinner filing density in this corpus. That does not guarantee those branches are unpatented elsewhere, but it does mean a first-mover claim there faces less immediately visible prior art within this specific dataset. Always confirm with a targeted freedom-to-operate search before filing.
247 of the 253 records in this corpus classify under G06F (electric digital data processing) versus 35 under H04L (digital information transmission). That split reflects the search's own IPC filter, which centres on G06F13's data-processing and I/O management logic — link training sequencing, error handling, lane management — rather than pure physical-layer transceiver design, which would more commonly sit in H04B or H04L. Readers focused on physical-layer signal design specifically should treat the H04L, H04B, and H03M subsets as the more relevant slice of this dataset.
Research PCIe and High-Speed Interconnect in depth with Eureka
Go past this page: query the whole pcie and high-speed interconnect corpus yourself, in your own scope.
Every answer comes back with patent numbers you can open.
Disclaimer. This page is generated from Patsnap Eureka data drawn from a limited snapshot of global patent and scientific-literature records, and is provided for general information and reference only.
Patent data carries inherent limitations: recent filings (typically the most recent 18–24 months) are under-counted due to standard publication lag; counts may be reported at either a patent-family or a patent-record basis and are not always directly comparable; classification, applicant-name, and citation data may contain errors, duplicates, or omissions; and the underlying search query defines and constrains the scope shown. As a result, the analysis may be incomplete or inaccurate and may not reflect the full technology landscape.
Nothing on this page constitutes an exhaustive prior-art, novelty, freedom-to-operate, or validity search, nor does it constitute legal, financial, investment, or professional advice, and it should not be relied upon as such. Any patent, commercial, or strategic decision should be verified independently and reviewed with qualified patent, legal, and domain professionals. Patsnap makes no warranties, express or implied, as to the accuracy, completeness, or fitness for any particular purpose of the information presented.
Machine translation. Assignee and organisation names originally recorded in Chinese, Japanese or Korean have been rendered into English by an AI translation step so that the tables stay readable. These renderings are best-effort and may not match a company’s registered English name; the original name is what the underlying patent record carries, and it is what any Eureka query launched from this page uses.