Phase Change Memory Crossbar Array Patents 2026
Phase Change Memory Crossbar Array Patents
PCM crossbar arrays have advanced from research demonstrations to production-relevant architectures. This dataset spans 2006–2026, covering cell engineering, 3D stacking, selector co-design, and AI accelerator integration.
PCM Crossbar Arrays: From Chalcogenide Switching to AI Integration
Phase change memory crossbar arrays organize PCM cells at the intersection of orthogonal wordlines and bitlines, achieving theoretical cell density approaching 4F²/layer. Switching relies on Joule-heating-induced transitions between a high-resistance amorphous RESET state and a low-resistance crystalline SET state in chalcogenide alloys, predominantly GeSbTe variants.
Within this dataset, the field spans four main technical sub-domains: cell structure engineering for reduced programming current and thermal isolation; 3D stacking and vertical integration architectures; selector and switch co-design for sneak-path suppression; and system-level integration of PCM arrays with CMOS logic for AI acceleration applications.
PCM’s core challenges—high RESET current, thermal crosstalk between adjacent cells, resistance drift in multilevel cell operation, and sneak path currents in selector-free arrays—have driven the dominant vectors of innovation across all assignees and time periods represented in this dataset. A simulated design showed a 32% reduction in reset current using GST nano-strip film arrays.
In this dataset, IBM is the single highest-volume assignee with at least 16 distinct patents, followed by YAMIC with at least 5 WO filings and Intel with at least 5 patents in retrieved records. US-jurisdiction patents dominate, representing approximately 70% of patents in this dataset, with WO filings at approximately 20%.
Filing Activity, Technology Clusters, and Jurisdictional Breakdown
The PCM crossbar dataset spans three distinct innovation phases from 2006 through 2026, with a visible acceleration in filings from 2022 onward. Technology cluster distribution in this dataset reflects shifting emphasis from foundational cell design toward 3D stacking and AI co-integration.
Patent Count by Technology Cluster — PCM Crossbar Array (Dataset Snapshot)
Cell structure engineering and 3D stacking are the two largest technology clusters in this dataset, each represented across at least five distinct assignees in retrieved records.
↗ Click bars to explorePCM Crossbar Patent Filings by Innovation Phase — Retrieved Records
Filing activity in this dataset accelerates sharply in the 2021–2026 phase, driven by YAMIC’s concentrated 2022 WO cluster and IBM’s continued BEOL integration and AI accelerator filings through 2025–2026.
↗ Click bars to exploreKey PCM Crossbar Application Areas Across the Dataset
PCM crossbar arrays in this dataset are deployed or targeted across four primary application domains: storage-class memory, AI and neuromorphic computing, embedded non-volatile memory for SoC, and peripheral consumer storage. Each domain is grounded in named patent filings and literature from the dataset.
Storage Class Memory (SCM)
Multiple patents across Intel, IBM, Seagate, Powerchip, and SK Hynix position PCM crossbar arrays as SCM filling the latency gap between DRAM and NAND flash. Seagate’s 2015 US patent describes tile-based cross-point resistive memory arrays coupled to a host controller for storage subsystem targeting. Powerchip’s 2024 vertical 3D XPoint patent explicitly cites SCM as its motivating application.
Storage ArchitectureAI and Neuromorphic Computing
IBM’s 2026 pending US patent exploits PCM resistance drift to erase hyperdimensional computing models for secure edge computing, reframing drift from a defect to a programmable property. IBM’s 2023 and 2024 AI accelerator patents co-integrate PCM for static weight storage with MRAM for frequently updated parameters within the same die. The 2021 literature survey frames PCM as a storage-to-computing technology transition enabler.
AI AccelerationEmbedded NVM for SoC
Intel’s 2022 US patent bonds a cross-point memory die face-to-face with a logic die via socket pad arrays, enabling high-bandwidth, low-latency access without off-chip interconnects for eNVM and eDRAM applications. IBM’s PCM+MRAM co-integration patents from 2023–2024 directly target SoC and AI chip applications. An earlier 130nm 1Mb embedded PCM demonstrated 500 kb/s single channel write throughput as proof of eNVM feasibility.
Embedded MemoryPeripheral Consumer Storage
Super Talent Technology’s 2011 US patent describes a high-speed controller for PCM-based MMC/SD peripheral devices, indicating consumer electronics storage applications in the earlier innovation phase. This represents the earliest application-layer commercialization signal in the dataset, predating the AI and eNVM convergence by over a decade.
Consumer StorageLeading Patent Assignees in PCM Crossbar Arrays — Dataset Snapshot
In this dataset, IBM is the highest-volume assignee with at least 16 patents spanning cell structure, 3D stacking, BEOL/FEOL integration, and AI acceleration, followed by YAMIC and Intel each contributing at least 5 filings in retrieved records. No single assignee’s share in this dataset should be interpreted as reflecting total industry output.
Top Assignees by PCM Crossbar Filing Count in Retrieved Records (Dataset Snapshot)
↗ Click bars to exploreInternational Business Machines
IBM holds at least 16 distinct patents in this dataset spanning 2018–2026, making it the highest-volume assignee in retrieved records. Key patents include the resistive liner stackable crossbar array (2020), single-sided liner PCM cell for 3D crossbar memory (2022), stacked cross-point phase change memory (2023 WO and 2025 US), BEOL crossbar array with crystallization front (2025), and AI accelerator patents co-integrating PCM and MRAM (2023–2024). IBM’s most recent 2026 US pending patent exploits PCM drift for hyperdimensional model erasure in secure edge computing.
United StatesYAMIC (Yangtze Advanced Memory)
YAMIC filed at least 5–6 WO-jurisdiction patents in 2022 alone, covering liner electrode cells, super-lattice cell structures, novel liner confined cell fabrication, vertical 3D PCM memory cells with OTS thin films, and replacement metal bit line/word line schemes for 3D X-Point memory. The WO filing strategy signals international patent protection intent. These filings address reduced programming current and inter-cell thermal crosstalk for 3D X-Point arrays, with national phase entries expected in the US, EP, KR, and JP jurisdictions.
China — WO FilingsFive Directional Signals from 2022–2026 PCM Filings
The most recent filings in this dataset (2022–2026) reveal five distinct directional signals, ranging from crystallization-front-controlled switching in BEOL to hybrid PCM+MRAM on-chip hierarchies for AI inference hardware.
Crystallization-Front-Controlled BEOL Switching
IBM’s 2023 and 2025 patents on crossbar arrays in both FEOL and BEOL configurations use crystallization seed layers with matched lattice constants to control switching uniformity without further lithographic scaling. The 2025 patent on crossbar memory array in back end of line with crystallization front describes epitaxial crystallization-front-controlled phase transitions. This represents a new materials-integration approach complementary to geometric cell scaling.
PCM Resistance Drift as a Functional Computing Resource
IBM’s 2026 pending US patent exploits differential drift rates between two PCM devices per cell to implement cryptographic model erasure for secure edge computing, reframing resistance drift from a liability to a programmable property. This paradigm shift—treating a historically problematic MLC reliability challenge as a functional mechanism—opens a new design space for privacy-preserving in-memory computation. Only IBM has filed in this area within this dataset.
IBM vs. YAMIC: Contrasting PCM Crossbar IP Strategies
Click any row to explore further.
| Dimension | IBM | YAMIC |
|---|---|---|
| Filing Count (Dataset) | At least 16 patents in retrieved records | At least 5–6 patents in retrieved records |
| Date Range | 2018–2026 (most recent 2026 pending US) | 2022 (concentrated WO cluster) |
| Primary Jurisdiction | US (dominant), WO counterparts for key structural patents | WO (international filing strategy) |
| Cell Structure Focus | Resistive liner, single-sided liner, multi-PCM-layer heat conductor stacks, crystallization seed layers | Liner confined cell, super-lattice cell, liner electrode cell — all targeting reduced RESET current and thermal crosstalk |
| 3D Architecture | Stacked cross-point (2023 WO, 2025 US), FEOL and BEOL crossbar integration | Vertical 3D PCM with continuous OTS thin films, replacement metal bit line/word line schemes |
| AI / Application Layer | PCM+MRAM AI accelerator (2023–2024), PCM drift for hyperdimensional model erasure (2026) | No AI application layer filings identified in this dataset |
| Selector Strategy | Crystallization-front control, BEOL integration pathways | OTS thin film continuous layers for vertical scaling |
| Strategic Signal | Broadest recent IP position; application convergence toward edge AI and heterogeneous memory hierarchies | Concentrated 2022 WO cluster signals international protection intent; national phase entries in US/EP/KR/JP expected |
Frequently Asked Questions: Phase Change Memory Crossbar Arrays
PCM crossbar arrays rely on Joule-heating-induced transitions between a high-resistance amorphous (RESET) state and a low-resistance crystalline (SET) state in chalcogenide alloys, predominantly GeSbTe (GST) variants. The transition is triggered by the current applied through the orthogonal wordline and bitline conductors at the cell intersection.
In a crossbar array without transistors at each cell, unselected cells along shared wordlines and bitlines create parasitic current paths called sneak paths that corrupt read operations. Approaches in this dataset include selector elements such as ovonic threshold switches (OTS), GlobalFoundries’ use of PCM itself as a selector exploiting its high ROFF/RON ratio (≥10⁴), Intel’s reference and sense architecture, and SK Hynix’s two-stage sensing scheme. Literature also shows approximately 20% sneak path current reduction using bilayer RRAM stacks.
In this dataset, IBM (International Business Machines Corporation) is the single highest-volume assignee with at least 16 distinct patents spanning 2018–2026, covering cell structure, 3D stacking, BEOL/FEOL integration, AI acceleration, and the most recent 2025–2026 filings. This count reflects retrieved records only.
YAMIC (Yangtze Advanced Memory Industrial Innovation Center) filed at least 5–6 WO-jurisdiction patents in 2022 alone covering liner electrode cells, super-lattice cells, vertical 3D PCM memory cells with OTS thin films, and replacement metal bit line/word line schemes. The WO filing strategy signals international patent protection intent and technology export ambitions, with national phase entries expected in the US, EP, KR, and JP jurisdictions.
IBM’s 2026 pending US patent exploits differential drift rates between two PCM devices per cell to implement cryptographic model erasure for secure edge computing hyperdimensional models. This reframes resistance drift—historically a reliability liability in multilevel cell PCM—as a programmable property for privacy-preserving in-memory computation.
US-jurisdiction patents dominate, representing approximately 70% of patents in this dataset, followed by WO filings at approximately 20%. EP and IN filings each represent smaller portions. No CN-jurisdiction PCM crossbar patents appear among the primary technical filings in this dataset, though YAMIC’s WO filings originate from a China-based assignee.
Data and insights on this page are based on a limited patent and literature dataset and are for reference only. Figures may not represent the complete technology landscape.