Physical Design & Place-and-Route Patents: Who Leads, Gaps 2026
- Filing has cooled since a 2020 peak of 8 families, with the 2022 midpoint at just 3 — this is a flat-to-declining filing curve, not a growth story.
- The most-cited records are two decades old, led by a standard-cell library tool suite cited 82 times, so today's applicants are building on well-worn foundations rather than untested ground.
- US filings dominate at 31 of the tracked records, with Europe, WIPO, the UK, India and Canada together accounting for the rest — filing strategy here is still US-centric.
Top-5 share is the combined record count of the five largest assignees divided by all 55 records in scope (CR5), not by the ranked leaders only.
What this patent set covers
This landscape tracks patent families at the intersection of physical design EDA, place-and-route and chip floorplanning, narrowed to filings that explicitly address timing closure, congestion, power grid design, clock tree synthesis or design rule checking. The IPC scope spans G06F30 (computer-aided design), G06F119 (design constraints) and H01L27 (integrated circuit devices), which pulls in both the software methodology side and the physical semiconductor structures it produces.
The dataset holds 55 published patent families across a filing window from 2015 through mid-2026. Because publication typically lags filing by around 18 months, the most recent one to two years in any trend chart will read lower than eventual filing volume — a normal artefact of the pipeline, not a sign that activity has already stopped.
Filing trends and technology composition
Two views of the same 55-family dataset: how filing volume has moved year over year, and how those families distribute across IPC subclasses.
A peak in 2020, then a decline
Filings ran at 6 in 2017, rose to a peak of 8 in 2020, and fell back to 3 by the 2022 midpoint. With 2026 showing 0 (a partial, still-publishing year), the visible curve is flat to declining rather than expansionary — this looks like a mature, well-claimed corner of EDA rather than an emerging one.
Software methods dominate, semiconductor structure claims follow
G06F carries all 55 records, confirming the corpus is anchored in computer-aided design methodology. H01L (24 records) and the newer H10D semiconductor-device subclass (11 records) show a substantial share of filings also stake out the physical device structures those methods produce. G06N (AI-based computing), H03K (logic circuits) and G05F (variable control) each register only a handful of records, marking them as thin, exploratory branches rather than established filing areas.
Shares are the percentage of the 55 records in scope. A patent can carry several IPC classes, so the shares add up to more than 100%.
Go deeper on Physical Design and Place-and-Route with Eureka
This page is one run against one query. Ask Eureka your own question about physical design and place-and-route and every answer comes back with the patent numbers behind it.
Try EurekaThe most-cited prior art in this space
Testing System and Testing Method (US10776558B2)
Filed by Global Unichip (Nanjing), this patent describes a testing method that runs a place-and-route procedure against a netlist to generate first layout data, then determines whether to replace a flip-flop circuit with a gated flip-flop circuit to produce second layout data, before testing the chip against that second layout data.The claim ties test methodology directly to a place-and-route output, linking physical design data to downstream chip verification.
| # | Publication no. | Patent title | Citations |
|---|---|---|---|
| 1 | US6539533B1 | Tool suite for the rapid development of advanced standard cell libraries | 82 |
| 2 | US5917729A | Method of and apparatus for placing and routing elements of semiconductor integrated circuit having reduced d… | 61 |
| 3 | US10783292B1 | Automated analog layout | 51 |
| 4 | US6948145B2 | Tool suite for the rapid development of advanced standard cell libraries employing the connection properties … | 31 |
| 5 | US20030121019A1 | Tool suite for the rapid development of advanced standard cell libraries | 30 |
| 6 | US6560753B2 | Integrated circuit having tap cells and a method for positioning tap cells in an integrated circuit | 28 |
| 7 | US20020108095A1 | Access cell design and a method for enabling automatic insertion of access cells into an integrated circuit d… | 23 |
| 8 | US6684377B2 | Access cell design and a method for enabling automatic insertion of access cells into an integrated circuit d… | 14 |
| 9 | US11636388B1 | Machine learning-based algorithm to accurately predict detail-route DRVS for efficient design closure at adva… | 12 |
| 10 | US20210117601A1 | Machine-learning enhanced compiler | 7 |
Citation counts reflect influence inside this searched corpus and skew toward older filings; they are not a measure of a patent's current commercial weight.
Each row carries its publication number; clicking a row searches Eureka by that number.
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Read together, the filing trend, citation pattern and IPC spread point to a field where the foundational claim space is occupied and current activity is thinner than the historical peak.
Momentum has cooled from its 2020 high
Filing volume rose steadily to a peak of 8 families in 2020, then dropped through the 2022 midpoint of 3. Given the usual 18-month publication lag, 2025-2026 figures will fill in somewhat, but the multi-year decline through the midpoint is a real signal, not a data artefact.
Influence sits with decades-old standard-cell tooling
The most-cited record, a standard cell library development tool suite cited 82 times, and its related filings on pin placement and net connection properties, anchor much of the citation graph. New entrants are building on infrastructure laid down well before the current filing window opened.
Filing strategy remains heavily US-anchored
The United States receives more than half of tracked filings (31), with Europe (10) a distant second and WIPO PCT, UK, India and Canada each in single digits. Applicants prioritising this space have concentrated protection domestically rather than building broad multi-jurisdiction coverage.
AI-assisted physical design is barely claimed yet
Every record touches G06F (computer-aided design), but only 4 records reach into G06N, the AI-model computing subclass. Combined with G05F's 3 records, this suggests learning-based approaches to place-and-route, congestion prediction or power grid optimisation remain a small fraction of filed claims relative to conventional methodology.
Eureka can read the same corpus for gaps instead of for coverage: under-claimed branches adjacent to physical design and place-and-route, with the prior art for and against each one.
Assignee landscape and where the gaps sit
Filing here spans semiconductor IP vendors, chip designers and toolmakers, but recent-year momentum has gone flat across the named assignees tracked — none show fresh filings in the latest year, consistent with the overall filing decline.
No assignee shows fresh recent-year filings
Every assignee in the recent-momentum tracking, including Qualcomm, AMD, Synopsys, HP Development, Fujitsu and CoreLogix, shows zero filings in the latest tracked year. This flat reading across the board matches the broader filing decline rather than pointing to any single company pulling back.
A moderate, tool-vendor-heavy corpus
At 55 families, this is a tightly scoped dataset rather than a sprawling one. The mix leans toward EDA tool vendors and semiconductor IP holders whose earliest filings established standard-cell and place-and-route methodology now cited across the field.
Protection strategy centres on the US market
With 31 of 55 records filed through the US receiving office, assignees here have prioritised US protection over broad international coverage. Secondary filing through EPO and WIPO PCT routes exists but at far lower volume.
| Assignee | Recent year | YoY |
|---|---|---|
| Qualcomm Incorporated | 0 | — |
| Advanced Micro Devices (AMD) | 0 | — |
| Synopsys, Inc. | 0 | — |
| Hewlett-Packard Development Company, L.P. | 0 | — |
| Fujitsu Limited | 0 | — |
| CoreLogix Ltd. | 0 | — |
| Hewlett-Packard Company | 0 | — |
| International Business Machines Corporation (IBM) | 0 | — |
Where to take this analysis
The dataset points to a mature core with a thin AI-assisted layer forming at the edges. Two follow-ups are worth running before committing filing budget.
Check freedom-to-operate against the top-cited families
The highest-cited records, several tied to standard-cell library tooling, sit at the centre of this landscape's citation graph. Any new filing touching pin placement, net connection properties or standard-cell generation should be checked against these before drafting claims.
Run a citation check in EurekaModel the AI-assisted design gap directly
With only 4 of 55 records reaching into G06N, learning-based approaches to congestion, timing or power grid prediction remain lightly claimed. A first-mover claim drafted around a specific ML technique applied to one of these physical design problems has room to stand on its own.
Explore white space in EurekaCommon questions about physical design patents
These are patents covering the methods and tools used to convert a logical chip design into a physical layout, including placement of standard cells, routing of interconnects, clock tree synthesis, power grid design and the checks that follow such as timing closure, congestion analysis and design rule checking. This dataset scopes that space using IPC classes G06F30, G06F119 and H01L27, combined with keyword filters on the specific technical operations. It excludes purely logical or behavioural design patents that never touch physical layout.
The filing trend in this dataset shows a rise to 8 families in 2020 followed by a drop to 3 by the 2022 midpoint and near zero by 2026. Part of that recent drop is a publication-lag artefact — patents filed in 2025 and 2026 typically haven't published yet, so those years will always look artificially low at the time of any snapshot. The decline through 2022, however, is a genuine signal that core place-and-route methodology claims may already be well staked out, pushing new activity toward adjacent or higher-level techniques rather than the foundational methods themselves.
The most-cited records in this corpus centre on standard cell library development tooling, with one family cited 82 times and a related filing on pin placement cited 31 times. These are older, foundational patents rather than recent filings, and citation count favours age within a searched corpus, so high citation counts here indicate historical influence on the field's methodology rather than current market share. Checking the assignee ranking table alongside recent-year momentum gives a more current picture of who is actively filing now versus who built the foundation.
Yes, based on the IPC composition: while every record in this dataset touches G06F (general computer-aided design), only 4 of 55 reach into G06N, the AI-model computing subclass, and only 3 touch G05F for variable control. That gap suggests machine-learning approaches to congestion prediction, power grid optimisation or clock tree synthesis are thinly claimed relative to conventional rule-based and heuristic methods. A first claim in one of these branches should be narrow and technique-specific rather than a broad claim to 'AI-assisted physical design,' which risks running into prior art on general EDA automation.
Of the 55 tracked records, 31 were filed through the US receiving office, with Europe (EPO) a distant second at 10, and WIPO PCT, UK, India and Canada each accounting for single digits. This US-heavy split means that companies operating primarily outside the US, or planning to manufacture and sell there, may find comparatively more freedom to operate under non-US patent regimes for the same techniques. It also means a company filing only in the US and via PCT hasn't necessarily secured broad international protection, which is worth checking before assuming a technique is blocked globally.
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Disclaimer. This page is generated from Patsnap Eureka data drawn from a limited snapshot of global patent and scientific-literature records, and is provided for general information and reference only.
Patent data carries inherent limitations: recent filings (typically the most recent 18–24 months) are under-counted due to standard publication lag; counts may be reported at either a patent-family or a patent-record basis and are not always directly comparable; classification, applicant-name, and citation data may contain errors, duplicates, or omissions; and the underlying search query defines and constrains the scope shown. As a result, the analysis may be incomplete or inaccurate and may not reflect the full technology landscape.
Nothing on this page constitutes an exhaustive prior-art, novelty, freedom-to-operate, or validity search, nor does it constitute legal, financial, investment, or professional advice, and it should not be relied upon as such. Any patent, commercial, or strategic decision should be verified independently and reviewed with qualified patent, legal, and domain professionals. Patsnap makes no warranties, express or implied, as to the accuracy, completeness, or fitness for any particular purpose of the information presented.
Machine translation. Assignee and organisation names originally recorded in Chinese, Japanese or Korean have been rendered into English by an AI translation step so that the tables stay readable. These renderings are best-effort and may not match a company’s registered English name; the original name is what the underlying patent record carries, and it is what any Eureka query launched from this page uses.