Power Delivery Noise in AI Accelerator Boards — PatSnap Eureka
Power Delivery Noise Reduction in AI Accelerator Boards
As AI workloads exceed 700W per accelerator card, managing power distribution network noise has become a first-order design challenge. This landscape covers patent and literature signals from 1991 to 2025 — spanning active filtering, resonance-aware scheduling, and the emerging frontier of workload-coupled PDN control.
Three Core Noise Phenomena Drive PDN Design Complexity
Power delivery noise in AI accelerator boards arises from the interaction between rapidly switching compute loads and the impedance of the power distribution network — a hierarchy spanning voltage regulator modules (VRMs), PCB power planes, package interconnects, and on-die power rails. The core technical problem is consistently framed around three phenomena: voltage droop from sudden current demand spikes (di/dt), PDN resonance at characteristic frequencies where inductive and capacitive elements interact destructively, and simultaneous switching noise (SSN) when multiple lanes or execution units toggle in concert.
As AI workloads grow denser and more power-hungry — often exceeding 700W per accelerator card — managing power distribution network (PDN) noise has become a first-order design challenge. Approaches span from passive filtering and decoupling capacitor placement, to active noise cancellation circuits, to firmware-level workload throttling and resonance-aware scheduling. The most recent filings (2019–2025) show a clear shift toward closed-loop, software-defined PDN management specifically contextualized for accelerator and AI chip architectures.
This landscape draws on patent and literature records from PatSnap’s IP analytics platform, covering filings from 1991 to 2025. It represents a snapshot of innovation signals within this dataset and should not be interpreted as a comprehensive view of the full industry. For authoritative standards context, see IEEE and JEDEC publications on power integrity.
Three Phases of PDN Noise Innovation: 1991 to 2025
The field has evolved from chip-level I/O driver noise suppression to AI-accelerator-specific closed-loop workload management, with a clear inflection point after 2019.
Four Technology Clusters Addressing PDN Noise
From active filtering to staggered switching, the patent landscape reveals four distinct engineering strategies — each targeting a different point in the noise generation and propagation chain.
Active and Closed-Loop PDN Filtering
A controller continuously measures voltage noise or a proxy metric such as bit error rate, then actuates variable filter elements to maintain noise within a target envelope. Amazon’s 2025 patent — the most AI-accelerator-specific filing in the dataset — applies workload-specific preset configurations before execution begins, then uses closed-loop monitoring to fine-tune in real time. IBM’s supplemental current supply approach cancels noise at the load by providing additional current from a dedicated second supply path when variation on the primary path is detected. See also PatSnap solutions for cross-domain PDN research.
Amazon 2025 · IBM 2019 · Intel 2006Resonance-Aware Workload Scheduling
Rather than filtering noise after it occurs, these approaches predict or detect resonant conditions and alter workload execution to avoid exciting resonant frequencies. Google’s 2022 patent detects when performance management operations such as clock swallowing or zero ops are applied at intervals that excite PDN resonance, then modifies the periodicity or nature of those operations. IBM’s local detection loop architecture deploys per-unit voltage noise sensors within a processor core, enabling fine-grained, spatially resolved throttling. This approach is particularly valuable for accelerator boards where the PDN is fixed in silicon but firmware can modulate execution patterns. For broader context, see IEEE power integrity standards.
Google 2022 · IBM 2021 · IBM 2007System-Level PDN Architecture and Impedance Engineering
This cluster focuses on the structural design of the PDN — how package, PCB, and on-die elements are organized and parameterized to suppress noise across the full impedance spectrum. GlobalFoundries’ 2013 patent defines voltage compression limits at each PDN layer (die, package, PCB) and restructures the network if any layer’s compression exceeds its limit. Georgia Tech’s power transmission line approach inserts a one-dimensional PTL between VRM and LDO to create a resonance null precisely in the frequency range where LDO power supply rejection peaks. Micron’s on-die anti-resonance structure uses on-die decoupling capacitors tuned to resonate with parasitic interconnect inductance to flatten the PDN impedance profile. Resources at PatSnap Analytics cover impedance engineering IP landscapes.
GlobalFoundries 2013 · Georgia Tech 2019 · Micron 2007Staggered Switching and Port-to-Port Delay
This cluster reduces simultaneous switching noise by introducing controlled temporal offsets between switching events so that their di/dt contributions do not superimpose constructively. Intel’s 2011 patent determines the resonant frequency of the PDN, derives an optimal inter-port delay of approximately 32 unit intervals at ~100 MHz resonance, and staggers lane power-on sequences accordingly. Microsoft’s dynamic power routing patent routes power from idled components specifically to support accelerator burst demands, with predictive pre-staging of power availability before a workload spike arrives. Intel’s multi-criteria pooled accelerator management redirects power between accelerators in a pool based on real-time telemetry. The principle of staggered activation is directly applicable to modern multi-chiplet AI accelerator packages. See JEDEC standards for switching noise specifications.
Intel 2011 · Microsoft 2020 · Intel 2019Filing Activity and Jurisdiction Distribution
Patent filing patterns across phases and jurisdictions reveal where PDN noise innovation is concentrated and where coverage is expanding.
Filing Phase Distribution
The AI-accelerator-specific phase (2019–2025) contains the most strategically significant filings, including Amazon’s 2025 workload-coupled PDN controller.
Jurisdiction Coverage
US jurisdiction dominates the dataset; EP and WO filings appear predominantly for Intel, while CN shows growing engagement from both multinationals and domestic assignees.
Five Converging Trajectories Shaping PDN Noise in 2025
The most recent filings (2019–2025) reveal a convergence toward predictive, software-defined, and AI-workload-aware PDN management strategies.
Workload-Coupled PDN Control (2025)
Amazon’s 2025 patent introduces applying a workload-specific preset configuration before execution begins, then using closed-loop monitoring to fine-tune in real time. This “predictive + reactive” two-phase model is directly tailored to AI inference workloads with known computation graphs and represents the leading edge of the dataset.
Per-Layer Neural Network Power Metering (2023–2024)
Axis AB’s filings capture per-layer power measurements in multi-layer networks, enabling the power management system to anticipate which network layers will create high di/dt events and pre-emptively reduce clock frequency. This granularity — below the chip level, at the neural network layer level — is described in the dataset as a significant architectural advance.
Resonance-Aware Scheduling as a Software Primitive (2019–2022)
Google’s resonance-aware performance management patents establish that PDN resonance avoidance can be implemented as a software/firmware primitive rather than requiring hardware redesign. This is particularly valuable for accelerator boards where the PDN is fixed in silicon but firmware can modulate execution patterns.
Where PDN Noise Patents Apply and What They Mean for R&D Teams
| Domain | Key Assignees | Core Mechanism | Strategic Signal |
|---|---|---|---|
| AI Accelerators & Neural Network Hardware | Amazon, Axis AB | Workload-specific PDN preset; per-layer clock frequency reduction | Hyperscalers building proprietary PDN intelligence into custom silicon — assess FTO exposure |
| Cloud & Data Center Compute | Microsoft, Intel | Dynamic power routing; multi-criteria pooled accelerator management | Rack-level and data-center-scale accelerator deployments sharing a common power budget |
| High-Speed I/O & Interconnects | Intel, Georgia Tech | Port-to-port delay ~32 unit intervals at ~100 MHz resonance; LDO-PTL bandwidth enhancement | PCI-E, CSI, FBD interfaces on AI accelerator boards connecting GPU/TPU dies to host CPUs |
Power Delivery Noise in AI Accelerators — key questions answered
Power delivery noise in AI accelerator boards arises from the interaction between rapidly switching compute loads and the impedance of the power distribution network. The core technical problems are: voltage droop from sudden current demand spikes (di/dt), PDN resonance at characteristic frequencies where inductive and capacitive elements interact destructively, and simultaneous switching noise (SSN) when multiple lanes or execution units toggle in concert.
Resonance-aware scheduling detects when performance management operations such as clock swallowing or zero ops are applied at intervals that excite PDN resonance, then modifies the periodicity or nature of those operations to avoid stimulating resonance. Google’s 2022 patent establishes that PDN resonance avoidance can be implemented as a software/firmware primitive rather than requiring hardware redesign.
Amazon’s 2025 Intelligent power noise reduction patent applies workload-specific preset configurations to PDN active filtering components before execution begins, then monitors voltage noise and bit error rate to dynamically adjust filter elements in real time. This predictive plus reactive two-phase model is directly tailored to AI inference workloads with known computation graphs.
Georgia Tech Research Corporation’s patents describe inserting a one-dimensional power transmission line (PTL) between the VRM and LDO to create a resonance null precisely in the frequency range where LDO power supply rejection peaks, enabling high efficiency and low noise simultaneously. This is highly relevant for the dense power rails on AI accelerator PCBs.
In this dataset, Intel Corporation is the most prolific assignee with at least 8 distinct patent records spanning US, EP, WO, MY, and CN jurisdictions. International Business Machines Corporation holds at least 3 active records across US, WO, and GB jurisdictions. Google LLC holds 2 US active records on resonance-aware scheduling, and Amazon Technologies holds the most recent AI-accelerator-specific filing from 2025.
Axis AB’s 2023–2024 patents implement per-layer power consumption measurement in multi-layer neural networks, with clock frequency reduction triggered by per-layer power criteria. This granularity — below the chip level, at the neural network layer level — enables the power management system to anticipate which network layers will create high di/dt events and pre-emptively reduce clock frequency.
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