This dataset identifies 202 patent families published between 2015 and mid-2026 that combine quantum annealing or adiabatic quantum computing terminology with design-optimization concepts like minor embedding and annealing schedule tuning, filtered to IPC classes G06N10/60, G06F30 and G06N10. That is a narrow, deliberately scoped slice of the wider quantum computing patent landscape, not a count of all quantum computing patents. The true current total is somewhat higher because publication typically lags filing by around 18 months, so the most recent years are undercounted.

The most-cited prior art in this corpus traces to D-Wave Systems, whose hybrid quantum-digital processor and calibration patents from 2009 onward anchor the field's citation base, with named inventors Harris, Berkley and Amin appearing repeatedly as co-assignees. Nokia Technologies also holds a notable method-level filing from 2015 covering core adiabatic annealing steps. Notably, every organisation tracked in this dataset, including these two, shows zero filings in the most recent tracked year, consistent with the broader plateau in filing activity.

Filings rose from 3 in 2017 to a peak of 22 in 2023, with the 2022 midpoint at 13, showing a real run-up over that period. Since the 2023 peak there has been no further acceleration, and recent-year momentum across every tracked assignee sits at zero. This looks more like a plateau than sustained growth, though the most recent one to two years are always undercounted because of publication lag, so a firmer read will only be possible in a year or two.

In this corpus, G06F (electric digital data processing) covers 72 records and H10N (other electric solid-state devices) covers 71, an almost even split. That means algorithmic claims, such as annealing schedule or chain strength tuning methods, occupy roughly the same claim territory as physical qubit and device-level claims. A freedom-to-operate review in this space needs to clear both layers rather than assuming one dominates, and smaller adjacent classes like H01L semiconductors and B82Y nanotechnology add further hardware-side density.

Based on classification and abstract density in this dataset, chain strength auto-tuning heuristics, minor embedding for sparse hardware graphs, and mid-run annealing schedule adaptation show thinner claim coverage than the core hybrid-processor and calibration art. The commercial-application layer, reflected in the relatively small G06Q count of 13, also looks under-claimed relative to the algorithmic and device layers. Any of these would need a fresh prior-art pull before drafting, since thinner density in a 202-family corpus is a starting signal, not a guarantee of clear space.