Rapid Thermal Processing Patents: Who Leads, Where the Gaps Are 2026
- 41.5% of all 123 records sit with just five assignees, so the core ramp-rate and uniformity claim space is already occupied at the top.
- Filing has been flat, not falling growth from 2021 to 2024 sits at 0% on the last complete years — the field has plateaued rather than declined, and 2025-26 figures are still filling in under normal publication lag.
- H01L and H10P dominate at 64.2% and 57.7% of records respectively, while crystal growth (C30B) and coating (C23C) classes sit far thinner — a signal of where claim space is still open.
Filing growth compares 2021 (1 records) with 2024 (1) — a three-year span. 2024 is the most recent year we treat as complete: publication lags filing by roughly 18 months, so 2025 onwards are still filling in and any growth rate that ends there would understate the field. Top-5 share is the combined record count of the five largest assignees divided by all 123 records in scope (CR5), not by the ranked leaders only.
What the rapid thermal processing uniformity patent record shows
Rapid thermal annealing and spike-anneal processes depend on tight control of ramp rate, chamber emissivity and pyrometer calibration to avoid slip dislocation and hold wafer-to-wafer repeatability. The patent record searched here spans 123 published records filed between 2015 and mid-2026, drawn from claims and descriptions that name ramp rate, temperature uniformity, pyrometer calibration, slip dislocation, chamber emissivity or repeatability directly. That scoping keeps the set to filings that engage with uniformity as a stated problem, rather than every RTA-adjacent equipment patent.
Filing concentrates in semiconductor device fabrication (H01L) and a closely related processing subclass (H10P), with a smaller but persistent presence in crystal growth and coating classes. The leader in the assignee ranking holds a wide margin over the rest of the field, and the drop from fifth to tenth place is steep — this is a landscape with a dense core and a long, thin tail.
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Filing trends and technology composition
The following views cover all 123 records in scope, drawn from receiving offices led by the United States, WIPO/PCT filings and China.
A plateaued filing curve
Annual filings peaked so far at 4 in 2023. Measured on the last two complete years, 2021 to 2024 growth sits at 0% — flat rather than declining. Treat 2025 and 2026 counts as incomplete: publication typically lags filing by around 18 months, so the most recent years always understate real activity.
Concentration in two adjacent classes
H01L (semiconductor devices) appears in 64.2% of the 123 records and H10P in 57.7%, confirming that most filings frame uniformity control as a device-fabrication or process-tooling problem. Crystal growth (C30B, 22.8%), coating and surface deposition (C23C, 9.8%) and memory device manufacture (H10B, 5.7%) are present but comparatively thin, and photolithography (G03F, 4.1%) barely registers — each is a candidate area to check before assuming freedom to operate.
Shares are the percentage of the 123 records in scope. A patent can carry several IPC classes, so the shares add up to more than 100%.
Go deeper on Rapid Thermal Processing Uniformity with Eureka
This page is one run against one query. Ask Eureka your own question about rapid thermal processing uniformity and every answer comes back with the patent numbers behind it.
Try EurekaThe most-cited records in this landscape
Argon/ammonia rapid thermal annealing for silicon wafers, silicon wafers fabricated thereby and czochralski pullers for manufacturing monocrystalline silicon ingots (US20010055689A1)
A silicon wafer is provided having controlled distribution of defects, in which denuded zones having a sufficient depth inward from the surface of the wafer are combined with a high gettering effect in a bulk region of the wafer. In the silicon wafer, oxygen precipitates, which act as intrinsic gettering sites, show vertical distribution. The oxygen precipitate concentration profile from the top to the bottom surfaces of the wafer includes first and second peaks at first and second predetermined depths from the top and bottom surfaces of the wafer, denuded zones between the top and bottom surfaces of the wafer and each of the first and second peaks, and a concave region between the first and…Abstract truncated as published; filed by Samsung Electronics, dated 2001-12-27.
| # | Publication no. | Patent title | Citations |
|---|---|---|---|
| 1 | US6366308B1 | Laser thermal processing apparatus and method | 159 |
| 2 | US20060018639A1 | Processing multilayer semiconductors with multiple heat sources | 157 |
| 3 | US5462898A | Methods for passivating silicon devices at low temperature to achieve low interface state density and low rec… | 92 |
| 4 | US20040130941A1 | Multibit metal nanocrystal memories and fabrication | 84 |
| 5 | US5904491A | Planar waveguides | 66 |
| 6 | US7259984B2 | Multibit metal nanocrystal memories and fabrication | 60 |
| 7 | US6030904A | Stabilization of low-k carbon-based dielectrics | 54 |
| 8 | US6897131B2 | Advances in spike anneal processes for ultra shallow junctions | 49 |
| 9 | US20010055689A1 | Argon/ammonia rapid thermal annealing for silicon wafers, silicon wafers fabricated thereby and czochralski p… | 41 |
| 10 | US20080090309A1 | Controlled annealing method | 36 |
Citation counts are drawn from within this searched corpus and favour older filings; treat them as a signal of influence on later work, not of current commercial weight.
Each row carries its publication number; clicking a row searches Eureka by that number.
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Browse MCP servers →What the numbers mean for a filing decision
Three patterns stand out once the ranking, trend and technology composition are read together.
The core claim space has a dense top
The leading assignee alone accounts for 25 records against a fifth-place figure of 6, and the top five combined hold 41.5% of all 123 records in scope. New entrants filing broad ramp-rate or pyrometer-calibration claims will run into this cluster first.
Flat, not declining
Filing counts moved from 1 in 2021 to 1 in 2024 — a flat trajectory rather than a shrinking one. Several of the largest historical filers show zero filings in the latest tracked year, which is consistent with a mature, plateaued core rather than an active land grab.
Adjacent classes are thinner
Semiconductor device claims (H01L) and the related processing subclass (H10P) dominate, while crystal growth, coating and memory-device manufacture classes each cover a smaller share of the same 123 records. That gap is where uniformity claims tied to specific process integrations are less contested.
Eureka can read the same corpus for gaps instead of for coverage: under-claimed branches adjacent to rapid thermal processing uniformity, with the prior art for and against each one.
Who holds the ramp-rate and uniformity claims
The assignee ranking returns 50 companies, spanning equipment makers, device manufacturers, wafer suppliers and one research foundation. Filing concentrates sharply at the top and thins quickly after tenth place.
A clear leader, then a steep drop
The top-ranked assignee holds 25 records against 6 at fifth place and 4 at tenth — a gap wide enough that the leader's filing choices effectively set the boundaries of the core claim space.
Established filers have gone quiet recently
Several of the historically largest assignees, including device makers, an equipment maker and a research foundation, show zero filings in the most recent tracked year. That is consistent with a plateaued field rather than one actively expanding at the top.
Co-filing is rare and narrow
Only five co-assignee pairs appear in the dataset, and the strongest recurring pairing links one equipment-side filer with a small set of individual co-inventors — collaboration here looks more like inventor teams than cross-company joint filing.
| Assignee | Recent year | YoY |
|---|---|---|
| Samsung Electronics Co., Ltd. (Korea) | 0 | — |
| Ultratech, Inc. | 0 | — |
| Advanced Micro Devices, Inc. | 0 | — |
| Cornell Research Foundation, Inc. | 0 | — |
| Genus, Inc. | 0 | — |
| Shin-Etsu Handotai Co., Ltd. | 0 | — |
| Seiko Epson Corporation | 0 | — |
| Applied Materials, Inc. | 0 | — |
Where to take this analysis
The dataset points to a plateaued, top-heavy field with specific thin spots. The next steps depend on whether the goal is freedom-to-operate, competitive tracking or identifying where to file.
Check freedom to operate against the top five
With 41.5% of all 123 records held by five assignees, any new ramp-rate, pyrometer-calibration or emissivity-compensation claim should be checked against this cluster before drafting.
Run a freedom-to-operate search in Eureka →Track quiet incumbents for renewed activity
Several top-ranked assignees show zero filings in the latest tracked year. A monitoring watch will catch the moment any of them resumes filing in this space.
Set up assignee monitoring in Eureka →Explore the thinner adjacent classes
Crystal growth, coating and memory-device manufacture classes carry far fewer records than the H01L/H10P core, which is where new claim scope is more likely to be available.
Explore white space in Eureka →Common questions on rapid thermal processing uniformity patents
The assignee ranking in this dataset of 123 records is led by a single company with 25 records, well ahead of the fifth-ranked assignee at 6. The top five assignees combined hold 41.5% of all 123 records, meaning a small group of equipment makers, device manufacturers and wafer suppliers control a disproportionate share of the ramp-rate, temperature-uniformity and pyrometer-calibration claim space. Anyone assessing freedom to operate should start with this cluster rather than the long tail of single-filing entrants that make up most of the ranked list.
On the last two complete filing years, growth from 2021 to 2024 sits at 0% — the field is flat rather than clearly growing or shrinking. The peak year so far is 2023 with 4 filings, and several of the largest historical assignees recorded zero filings in the most recent tracked year. Figures for 2025 and 2026 should be read as incomplete, since publication typically lags actual filing by around 18 months.
Most records classify under semiconductor devices (H01L, 64.2% of the 123 records) and a closely related processing subclass (H10P, 57.7%), meaning uniformity control is usually framed as part of device fabrication or process tooling. Crystal growth (C30B), coating and surface deposition (C23C), memory device manufacture (H10B) and photolithography (G03F) all appear but at much lower shares. Because a single record can carry multiple IPC classes, these percentages add up to more than 100%, and the thinner classes are worth checking as areas of lighter claim density.
The technology composition data points to crystal-growth-stage thermal uniformity, pyrometer calibration drift correction and multi-zone lamp control as areas with meaningfully fewer records than the dominant H01L and H10P classes. Co-assignee collaboration is also limited to just 5 identified pairs across the whole dataset, suggesting little cross-company joint filing exists to defend these adjacent branches. A first claim in one of these thinner areas is more likely to find open space than another filing squarely inside the core ramp-rate or temperature-uniformity claims already held by the leading assignees.
US20010055689A1, filed by Samsung Electronics and dated 2001-12-27, describes a silicon wafer with a controlled vertical distribution of oxygen precipitates and denuded zones, produced using an argon/ammonia rapid thermal annealing process and a modified Czochralski puller. It matters because it ties a specific gas-ambient RTA process directly to a defect-distribution outcome in the wafer, which is the kind of process-to-outcome claim that tends to sit upstream of later device and tooling patents. Anyone filing on gas-ambient control during rapid thermal annealing of silicon ingots or wafers should review its claims directly rather than relying on this summary.
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Disclaimer. This page is generated from Patsnap Eureka data drawn from a limited snapshot of global patent and scientific-literature records, and is provided for general information and reference only.
Patent data carries inherent limitations: recent filings (typically the most recent 18–24 months) are under-counted due to standard publication lag; counts may be reported at either a patent-family or a patent-record basis and are not always directly comparable; classification, applicant-name, and citation data may contain errors, duplicates, or omissions; and the underlying search query defines and constrains the scope shown. As a result, the analysis may be incomplete or inaccurate and may not reflect the full technology landscape.
Nothing on this page constitutes an exhaustive prior-art, novelty, freedom-to-operate, or validity search, nor does it constitute legal, financial, investment, or professional advice, and it should not be relied upon as such. Any patent, commercial, or strategic decision should be verified independently and reviewed with qualified patent, legal, and domain professionals. Patsnap makes no warranties, express or implied, as to the accuracy, completeness, or fitness for any particular purpose of the information presented.
Machine translation. Assignee and organisation names originally recorded in Chinese, Japanese or Korean have been rendered into English by an AI translation step so that the tables stay readable. These renderings are best-effort and may not match a company’s registered English name; the original name is what the underlying patent record carries, and it is what any Eureka query launched from this page uses.