An RDL is a patterned metal-and-dielectric structure built on top of a semiconductor die or package that reroutes bond pads to new locations, typically to spread I/O over a larger area for fan-out packaging or to align pads with a different substrate pitch. It is a packaging-level feature rather than a change to the underlying transistor structure. In this patent corpus, RDL claims are filed predominantly under H01L23/538 and H01L21/48, and most also carry the H10W packaging classification, reflecting how the industry now treats RDL as a packaging discipline rather than a purely device-level one.

The assignee ranking in this dataset is led by large integrated device manufacturers and specialist packaging houses, including Samsung Electronics, TSMC, Samsung Electro-Mechanics, Deca Technologies, Powertech Technology and Intel. All of these show zero filings in the most recent tracked year, which reflects both a genuine slowdown from the 2018 peak and the roughly 18-month lag between filing and publication that understates the latest year in any patent trend. A ranking that stays fairly concentrated, rather than long-tailed, suggests the field is dominated by a defined set of repeat filers rather than fragmented across many small entrants.

Activity has declined from its 2018 peak of 13 filed families to roughly half that by the 2022 midpoint, and the trend continues downward into the most recent years of the dataset. This does not mean innovation has stopped — publication lag means the newest filings are undercounted — but the decline through the middle years of the trend is real and suggests the foundational structure and process claims for basic RDL are largely occupied. New activity is more likely to concentrate in narrower variations, such as multi-tier RDL stacks or specific material systems, than in first-generation RDL structures.

US20250279404A1, assigned to Samsung Electronics, claims a semiconductor package with two stacked redistribution layers separated by a planarization layer, where the first RDL carries a chip under a molding layer with a recessed upper surface and the second RDL sits above the planarization layer. It is a multi-tier stacking and flatness-control claim rather than a claim over RDL wiring in general, so it is most relevant to designs that stack two or more RDL planes with an intervening planarization step. Anyone building a single-tier RDL structure, or a multi-tier stack without the specific molding-recess-plus-planarization arrangement, sits outside its narrowest claim scope, though a full claim chart is needed to confirm freedom to operate for any specific design.

The clearest gaps sit at the edges of the core H01L/H10W packaging classification: RDL structures that intersect waveguide or microwave routing (H01P), memory-device interconnect (H10B), and PCB-level redistribution assemblies (H05K) each show only one or two filings in this corpus, against 91 total families concentrated in core packaging claims. That thinness does not guarantee the space is legally open — it may simply be commercially unattractive — but it is a reasonable starting point for a novelty search before investing in a design in one of those adjacent branches. A dynamic via-clipping approach to panelized packaging, distinct from the heavily-cited existing method, is another area worth checking closely given how much prior art already cites the leading adaptive-patterning family.