Resistive RAM Compute-In-Memory Macro Technology 2026
Resistive RAM Compute-In-Memory Macro Technology 2026
RRAM-based CIM macros perform multiply-accumulate operations directly within crossbar arrays, eliminating von Neumann data-movement penalties. Retrieved records span 2011–2026, covering analog VMM, digital stateful logic, MLC programming, and hybrid RRAM–SRAM architectures.
RRAM CIM Macros: From Crossbar Physics to AI Inference
RRAM-based compute-in-memory macros exploit resistance-switching in metal-oxide dielectrics—most prominently HfO₂, HfAlOx, TiO₂, and chalcogenide systems—to store analog or multi-level weights and perform vector-matrix multiplication directly within crossbar or 1T1R array structures. Ohm’s law and Kirchhoff’s current law naturally implement MAC operations when wordline voltages encode input activations and cell conductances encode synaptic weights.
The field spans four primary sub-domains within this dataset: analog VMM macros using continuous conductance states, digital stateful in-memory logic executing Boolean operations (IMPLY, majority, XOR), multi-level cell storage demonstrated at up to 4 bits per cell using self-adaptive write termination, and 3D-stacked architectures with monolithic integration of RRAM layers above CMOS logic.
A landmark 2022 publication delivered a fully integrated RRAM-CIM chip achieving simultaneous high energy efficiency, multi-model versatility, and software-comparable accuracy—signaling transition toward productization. Applied Materials demonstrated an SoC with scalable RRAM tiles achieving MNIST classification accuracy matching simulation predictions, confirming a path to commercial edge AI accelerators.
Among the most recent filings (2024–2026) in this dataset, CN-jurisdiction assignees—Shanghai Jiao Tong University, South China University of Technology, NengXin Electronics, and Anhui University—constitute the majority of new macro-level CIM disclosures in retrieved records, reflecting a geographic shift in active innovation toward Chinese institutional filers.
CIM Macro Patent Trends: Jurisdictions and Technology Clusters
Retrieved records reveal a jurisdictional split between US and CN filings across four primary technology clusters, with the most recent 2024–2026 filings concentrated in hybrid RRAM–SRAM and all-digital CIM macro architectures filed under CN jurisdiction.
Patent Count by Jurisdiction (Dataset Snapshot)
CN-jurisdiction filings (9 records) narrowly exceed US filings (8 records) in this dataset, with EP and IN each contributing 2 records and WO contributing 1, reflecting a recent shift toward Chinese institutional assignees in the most current filing cohort.
↗ Click bars to explorePatent Records by Technology Cluster (Dataset Snapshot)
Analog crossbar VMM macros represent the largest single technology cluster in this dataset, followed by digital/stateful in-memory logic and MLC programming circuits, with hybrid and 3D integration architectures accounting for the most recently filed records.
↗ Click bars to exploreWhere RRAM CIM Macros Are Being Deployed
Retrieved records identify five distinct application domains for RRAM CIM macros, spanning edge AI inference, neuromorphic computing, satellite-borne image processing, network search acceleration, and general-purpose reconfigurable computing.
Edge AI Inference Acceleration
The dominant application domain in this dataset is edge AI inference for CNNs and binary neural networks. A 2022 RRAM-CIM chip demonstrated simultaneous high energy efficiency, multi-model versatility, and software-comparable accuracy. Applied Materials’ 2022 SoC with scalable RRAM tiles achieved MNIST classification accuracy matching simulation predictions, confirming a commercial edge AI accelerator path.
AI InferenceNeuromorphic Brain-Inspired Computing
RRAM’s analog conductance modulation mimics biological synaptic plasticity. Gate-controlled pulse programming for minimum conductance variation is evaluated as critical for analog neuromorphic weight fidelity. Forming-free HfO₂ crossbars demonstrated eigenvalue computation, eliminating a key reliability barrier for neuromorphic deployment. SiOx-enhanced RRAM synaptic devices were reviewed in a 2018 brain-inspired computing survey.
NeuromorphicSatellite Aerospace Edge Computing
Both January 2026 and March 2026 CN patents from Shanghai Jiao Tong University explicitly target low-earth-orbit (LEO) satellite remote sensing image processing, where radiation tolerance and ultra-low power are paramount. The hybrid RRAM–SRAM reconfigurable CIM system uses RRAM for non-volatile weight storage and SRAM for high-speed activation buffering, combining the strengths of both technologies within a single macro.
Satellite / AerospaceNetwork Search and TCAM Applications
Hewlett Packard Enterprise’s active US patent (2019) integrates RRAM with ternary content-addressable memory, enabling associative search directly coupled to resistive memory readout via 1T1R memristor bitcells. This is applicable to network packet classification and database lookup engines. A 2018 ReRAM architecture survey also identifies associative search as a core application domain for ReRAM-based processing-in-memory systems.
Network / SearchLeading Patent Assignees in RRAM CIM Macros — Dataset Snapshot
In this dataset, Qualcomm Incorporated holds the largest filing cluster with five patents across WO, CN, EP, US, and IN jurisdictions, while Intel Corporation holds three active or pending US patents filed between 2022 and 2026, making these two assignees the most prolific filers in retrieved records among identifiable assignees.
Top Assignees by Filing Count in Retrieved Records (Dataset Snapshot)
↗ Click bars to exploreQualcomm Incorporated
Qualcomm holds the largest patent cluster in this dataset with five filings across WO, CN, EP (2015 and 2016), US, and IN jurisdictions. All five filings cover integrated MRAM cache module architectures, focusing on MRAM-based last-level cache and main memory integration rather than RRAM-CIM macros per se. The filing activity spans multiple jurisdictions reflecting broad IP protection strategy.
United StatesIntel Corporation
Intel holds three active or pending US patents filed between 2022 and 2026 covering SRAM-based compute-in-memory macros using C-2C capacitor ladder analog computation schemes. The most recent filings include a January 2026 active patent and an April 2026 pending patent, both extending the same SRAM-based analog CIM macro architecture. Intel’s CIM focus in this dataset is on SRAM-analog approaches rather than RRAM-specific macros.
United StatesFour Forward-Looking Directions from 2023–2026 Filings
The most recent filings (2023–2026) in this dataset point to four identifiable forward-looking directions: hybrid RRAM–SRAM reconfigurable macros, time-domain CIM encoding, 2D material-based monolithic 3D integration, and fully reconfigurable all-digital CIM macros with dynamic logic.
Hybrid RRAM–SRAM Reconfigurable Macro Architectures
Both January 2026 and March 2026 CN patents from Shanghai Jiao Tong University describe systems combining RRAM non-volatile weight storage with SRAM high-speed activation buffering in a single reconfigurable macro targeting satellite-borne AI inference. This hybrid paradigm directly addresses RRAM write-endurance limitations and SRAM leakage power simultaneously. The explicit LEO satellite remote sensing target signals a vertical where no incumbent memory technology currently dominates.
Time-Domain CIM Encoding for MRAM and RRAM
An April 2026 CN filing from NengXin (Changzhou) Electronics Technology Co., Ltd. introduces time-domain encoding of MAC outputs as pulse-width or time differences rather than voltage amplitudes, bypassing traditional ADC bottlenecks. This approach offers potential power reduction for MRAM-based CIM macros and represents a departure from conventional voltage-mode analog CIM output encoding. The patent is currently pending in the CN jurisdiction.
Analog VMM vs. Digital Stateful In-Memory Logic: Key Dimensions
Click any row to explore further.
| Dimension | Analog VMM Macro (RRAM Crossbar) | Digital Stateful In-Memory Logic |
|---|---|---|
| Primary Operation | Vector-matrix multiplication (VMM) via Ohm’s law and Kirchhoff’s current summation on bitlines | Boolean logic (IMPLY, majority gate, XOR, NOR) executed by voltage pulses on RRAM cells |
| ADC Requirement | Peripheral ADCs required to digitize analog bitline currents — major area and energy cost | No ADC required — logic result read as resistance state change |
| Variability Tolerance | Sensitive to cycle-to-cycle HfO₂ conductance variation impacting precision | Strong variability resilience; logic state is binary (SET/RESET) |
| Parallelism | All wordlines asserted simultaneously for maximal parallelism (e.g. 128 wordlines in 128×64 XNOR-RRAM) | Up to 16 parallel operands demonstrated after 1 million endurance cycles in scouting logic |
| MLC Density | Up to 4 bits/cell (QLC) demonstrated with self-adaptive write termination in HfO₂ 1T1R cells | First MLC 2-bit in-memory adder demonstrated; density constrained by logic sequencing overhead |
| Operation Schedule | Single array access cycle for VMM; peripheral circuits handle input encoding | Carefully sequenced read-write operation schedules required for stateful logic execution |
| Target Application | CNN/DNN inference, BNN acceleration, neuromorphic weight storage | General-purpose in-memory arithmetic, RISC-V logic-in-memory (RISC-Vlim framework) |
| 3D Integration | Demonstrated in monolithic 3D with MoS₂ transistors in 1T–4R structure at sub-300 °C | Scalable 2T2R structure demonstrated in 3D stacked memory arrays with reconfigurable interconnects |
Frequently Asked Questions: RRAM Compute-In-Memory Macros
RRAM CIM macros store neural network weights as resistance states in crossbar or 1T1R array structures. Ohm’s law and Kirchhoff’s current law naturally implement multiply-and-accumulate (MAC) operations: wordline voltages encode input activations, cell conductances encode synaptic weights, and resulting currents sum along bitlines to perform vector-matrix multiplication in a single array access cycle.
A 2021 paper demonstrated quad-level cell (QLC) RRAM achieving 4 bits per cell using self-adaptive write termination that controls RESET compliance current in HfO₂ 1T1R cells. A separate 2021 work achieved eight distinct resistance states through compliance current control, eliminating the need for read-verify loops in MLC programming.
In this dataset, Qualcomm Incorporated holds the largest cluster with five filings across WO, CN, EP, US, and IN jurisdictions covering integrated MRAM cache module architectures. Intel Corporation holds three active or pending US patents (2022–2026) on SRAM-based CIM macros using C-2C capacitor ladder computation. Shanghai Jiao Tong University and Southern University of Science and Technology each hold two filings in retrieved records.
Both the January 2026 and March 2026 CN patents from Shanghai Jiao Tong University describe RRAM and SRAM hybrid reconfigurable compute-in-memory systems targeting low-earth-orbit (LEO) satellite remote sensing image processing, where radiation tolerance and ultra-low power are paramount.
A 2023 demonstration stacked MoS₂ transistors between bottom-plane and top-plane vertical RRAMs in a 1T–4R structure using a sub-300 °C fabrication process. This sub-300 °C thermal budget is significant because it removes the constraint that has historically prevented true monolithic 3D logic-memory integration on top of completed CMOS logic dies.
Conventional analog CIM macros digitize bitline currents using peripheral ADCs, which dominate macro area and energy budgets. The April 2026 CN filing from NengXin (Changzhou) Electronics Technology Co., Ltd. encodes MAC outputs as pulse-width or time differences rather than voltage amplitudes, bypassing traditional ADC bottlenecks and offering potential power reduction for MRAM-based CIM macros.
Data and insights on this page are based on a limited patent and literature dataset and are for reference only. Figures may not represent the complete technology landscape.