RRAM Security Primitives Patent Landscape 2026
RRAM Security Primitives: Patent Landscape 2026
Resistive RAM is emerging as a foundational substrate for PUFs, TRNGs, and encrypted memory architectures by exploiting stochastic resistive switching physics. This dataset spans patent and literature records from 2008 to 2026 across IoT, aerospace, and confidential computing domains.
How RRAM Physics Enables Hardware Security Primitives
Resistive RAM (RRAM/ReRAM) operates by forming and rupturing conductive filaments within thin dielectrics — typically HfO₂, TaOₓ, or TiO₂ — between two metal electrodes. The stochastic ionic migration processes governing set/reset transitions between high-resistance state (HRS) and low-resistance state (LRS) are the same variability sources that security designers exploit for entropy generation.
Four principal security functions are being built on RRAM physics in this dataset: Physical Unclonable Functions (PUFs) leveraging cell-to-cell resistance variation, True Random Number Generators (TRNGs) exploiting probabilistic switching dynamics, encrypted non-volatile storage using filament morphology or cipher integration, and tamper-evident or self-destructible memory using transient substrates or masked states.
The innovation timeline spans roughly 2008 to 2026, clustering across three phases: a Foundational Phase (2008–2016) focused on device physics and hybrid NV-SRAM architectures; a Development Phase (2017–2021) where RRAM PUFs, MRAM TRNGs, and serial concealment cells were experimentally validated; and an Acceleration Phase (2022–2026) pushing toward system-level integration with RISC-V secure enclaves and array-level entropy harvesting.
In this dataset, CN is the most represented jurisdiction by filing count (~12 records), dominated by academic institutions including Wuhan University and Shanghai Jiao Tong University. US filings (~8 records in retrieved records) come from semiconductor and system companies including Qualcomm, Intel, HP, PowerChip, and Agate Logic. Core RRAM security primitives remain concentrated in academic literature rather than granted patents in this dataset, suggesting incomplete commercial IP capture.
Filing Patterns and Technology Cluster Distribution
Within this dataset, RRAM security patent activity spans four identifiable technology clusters and shows clear phase-based growth from 2008 to 2026. The charts below reflect distribution patterns within retrieved records only.
Technology Cluster Distribution in This Dataset
RRAM PUF-related records form the largest cluster in this dataset, followed by encryption-augmented NVM and TRNG approaches, with radiation-hardened security cells forming a smaller but distinct group.
↗ Click bars to exploreFiling Activity Phase Distribution (Dataset Snapshot)
In this dataset, filing and publication activity accelerated sharply in the 2022–2026 phase, with system-level integration patents representing the most recent cluster of activity compared to earlier device-physics-focused records.
↗ Click bars to exploreKey Application Domains for RRAM Security Primitives
RRAM security primitives are being deployed across IoT authentication, trusted computing, aerospace, and enterprise storage. The following cards highlight the principal application domains identified across patents and literature in this dataset.
IoT and Embedded Authentication
RRAM PUF-based authentication is directly targeted at IoT terminal devices and RFID automation. A reconfigurable RRAM PUF integrated into a lightweight RFID mutual authentication protocol achieves near-ideal 50% inter-chip Hamming distance and a bit error rate as low as 3.8×10⁻⁶ (2021). Ternary PUF designs for terminal device content protection and session key recovery achieve sub-10⁻³ bit error rates without error-correcting codes (2022).
Embedded AuthenticationTrusted Computing and Confidential Cloud
Wuhan University holds CN patents (2016–2025) applying NVRAM security to virtual TPM (vTPM) protection using hardware transactional memory and RISC-V firmware TPM implementations combining DRAM-delay PUF-derived keys with NVRAM encrypted storage and rollback attack defense. A 2025 CN filing explicitly implements a RISC-V architecture firmware trusted platform module using PUF keys stored in NVRAM. These represent the leading Chinese academic patent cluster on NVM security system integration in retrieved records.
Trusted ComputingAerospace and Harsh-Environment Computing
ReRAM-integrated radiation-hardened latches are explicitly targeted at satellite and space environments. A 2022 literature study demonstrates ReRAM-integrated latches that simultaneously provide non-volatile state storage and complete SEU immunity for aerospace applications, reducing transistor count by 50% versus comparable solutions. SMART magnetoelectric antiferromagnet-based tamper-proof NVM targets on-chip dense secure NVM in harsh operating conditions (2020).
Aerospace ComputingEnterprise Storage and Cloud Infrastructure
Hewlett Packard Enterprise’s WO/US/EP patents (2015–2016) claim a hybrid NVM architecture for main memory combining memristors, PCRAM, and STT-RAM with encryption to prevent information extraction after power-down, targeting enterprise servers. A 2021 literature study on in-phase change memory data randomisation targets PCM-based cloud servers and multi-tenant systems for security enhancement.
Enterprise StorageKey Patent Assignees in RRAM Security Primitives (Retrieved Records)
In this dataset, Hewlett Packard Enterprise, Qualcomm Technologies, and Wuhan University each account for 3 distinct filings in retrieved records, representing the highest filing counts among named assignees. PowerChip Semiconductor and ASM IP Holding each contribute 2 filings in retrieved records, with Huawei and Intel each contributing 1–2 filings.
Top Assignees by Filing Count — RRAM Security Primitives (Dataset Snapshot)
↗ Click bars to exploreHewlett Packard Enterprise Development LP
Hewlett Packard Enterprise holds 3 filings across WO, US, and EP jurisdictions (2015–2016), representing the most geographically broad single-technology portfolio in this dataset. Their core patent family covers a hybrid NVM main memory architecture combining memristors, PCRAM, and STT-RAM with encryption to prevent information extraction after power-down. All three filings in retrieved records are directed to enterprise secure main memory, with the WO filing (2015) and subsequent US/EP grants forming the foundational family.
United StatesQualcomm Technologies, Inc.
Qualcomm Technologies holds 2 US filings (2019, 2020) and 1 TW filing (2018) in retrieved records, covering NV-resistance-element-based SRAM PUF circuits that replace pull-up or pull-down transistors with passive NV resistance elements to eliminate transistor noise and enhance PUF reproducibility. The 2020 US patent targets transistor noise-tolerant SRAM PUF circuits, while the 2019 US filing covers PUF memory employing SRAM bit cells with added passive resistance. These represent the most commercially mature security primitive integration from a semiconductor company in this dataset.
United StatesFive Emerging Directions in RRAM Security Primitives (2022–2026)
Based on the most recent filings and publications in this dataset (2022–2026), five convergent directions are shaping the next generation of RRAM-based hardware security. These range from system-level RISC-V integration to materials-physics-level filament encryption.
RISC-V + NVRAM Security Co-Design
Multiple 2024–2025 CN filings from Wuhan University converge on RISC-V as the open-source processor platform for NVM-secured trusted execution environments. A 2025 CN filing combines DRAM-delay PUF-derived keys with NVRAM encrypted storage and rollback attack defense — a converged system-level approach absent in earlier filings. Western incumbents are largely absent from this intersection in retrieved records, suggesting a potential freedom-to-operate risk for open-architecture secure processor products.
1T1R Array-Level Random Pattern Generation
Huawei’s 2024 EP filing (pending) claims simultaneous SET operations on N×M 1T1R RRAM device arrays followed by resistance value summation to generate random patterns, moving beyond single-device characterization toward array-integrated entropy harvesting. This approach directly targets both PUF and TRNG co-generation from the same array infrastructure. The filing represents a shift from device-level proof of concept toward scalable, array-wide security primitive generation in this dataset.
RRAM PUF vs. RRAM TRNG: Key Dimensional Comparison
Click any row to explore further.
| Dimension | RRAM PUF | RRAM TRNG |
|---|---|---|
| Primary Entropy Source | Cell-to-cell resistance variation from stochastic filament formation during fabrication | Probabilistic switching dynamics — stochastic HRS-to-LRS transition at given voltage pulse |
| Security Output | Challenge-response pairs that are device-unique and difficult to clone | Cryptographically random bit stream for key generation and nonce production |
| Key Metric | Inter-chip Hamming distance ~50%; bit error rate as low as 3.8×10⁻⁶ (RFID PUF, 2021) | 22 Mbit/s throughput validated against NIST SP-800-22 (MRAM TRNG, 2021) |
| Reliability Challenge | Unstable cells reduce reproducibility; ternary state masking addresses this without ECC | Switching stochasticity must be preserved; circuit must avoid deterministic bias |
| Representative Patent / Literature | Qualcomm US (2020): NV-resistance-element SRAM PUF; VCM ReRAM crossbar PUF (2018 literature) | Huawei EP (2024): 1T1R array simultaneous SET for random pattern generation; MRAM TRNG (2021 literature) |
| IP Maturity | Mix of academic literature and commercial patents (Qualcomm, Huawei); ternary approaches emerging 2022–2023 | Largely academic literature in dataset; Huawei 2024 EP pending represents most recent commercial filing |
| Application Focus | IoT/RFID authentication, content protection, session key recovery, SRAM-based root of trust | Cryptographic key generation, nonce production, TRNG-as-a-service in secure enclave contexts |
Frequently Asked Questions: RRAM Security Primitives Patents
RRAM’s stochastic ionic migration processes govern set/reset transitions between high-resistance state (HRS) and low-resistance state (LRS). The same filament formation randomness that challenges memory engineers as variability becomes an exploitable entropy source for PUF device fingerprinting and TRNG probabilistic switching, as described across multiple records in this dataset.
In this dataset, Hewlett Packard Enterprise Development LP, Qualcomm Technologies, and Wuhan University each have 3 distinct filings. ASM IP Holding B.V. and PowerChip Semiconductor Manufacturing Corporation each have 2 filings. Huawei Technologies and Intel each contribute 1–2 filings in retrieved records.
A ternary PUF tracks three cell states (1, 0, X) where X denotes unstable cells. Pre-forming range operations in ReRAM enable ternary PUF designs that mask unstable cells and achieve sub-10⁻³ bit error rates without conventional error-correcting codes, as demonstrated in 2022 and 2023 literature in this dataset.
Huawei’s pending EP patent (2024) claims simultaneous SET operations on N×M 1T1R RRAM device arrays followed by resistance value summation to generate random patterns, directly targeting PUF and TRNG co-generation from the same array infrastructure — moving beyond single-device characterization toward array-level entropy harvesting.
Multiple 2024–2025 CN filings from Wuhan University combine DRAM-delay PUF-derived keys with NVRAM encrypted storage and rollback attack defense on RISC-V as the open-source processor platform for trusted execution environments. This converged system-level approach was absent in earlier filings and Western incumbents are largely absent from this intersection in retrieved records.
Non-volatility itself is a security liability because data persists after power-off, making NVM susceptible to physical extraction attacks. Side-channel attack vulnerability is also comprehensively identified in the literature for MRAM, PCM, and RRAM. Serial RRAM cells with masked third states and filament morphology encoding address these risks, but patent-level countermeasures beyond encoding schemes are sparse in this dataset.
Data and insights on this page are based on a limited patent and literature dataset and are for reference only. Figures may not represent the complete technology landscape.