Ruthenium Interconnect Barrier Layer Patents 2026
Ruthenium Interconnect Barrier Layer Technology 2026
Ruthenium has emerged as the successor to Ta/TaN barrier systems in sub-5 nm BEOL interconnects, where traditional stacks consume an unacceptable fraction of conductive cross-section. This dataset spans foundational filings from 2001 through pending applications of 2025–2026.
Why Ruthenium Is Replacing Ta/TaN in Advanced Interconnects
Ruthenium addresses a fundamental scaling crisis in copper damascene metallization. As interconnect half-pitch approaches 20 nm and below, the conventional TaN/Ta bilayer must exceed 4 nm to maintain adequate barrier and liner properties, occupying a disproportionate fraction of the conductive cross-section and degrading effective conductance because TaN and Ta are far more resistive than copper.
Ruthenium, a platinum-group refractory metal with hexagonal close-packed crystal structure, offers bulk resistivity of approximately 7.6 μΩ·cm, strong copper wettability, compatibility with electroplating enabling direct copper deposition without a separate PVD seed layer, and robust diffusion barrier character. RuTa alloys orient to the Ru(002) plane, which has lower lattice mismatch with Cu(111) than Ta(110)/Cu(111), simultaneously improving wettability and barrier quality.
The technology spans four principal sub-domains: pure ruthenium liners and caps in dual damascene structures; ruthenium alloyed with tantalum (RuTa) or doped with nitrogen (RuTaN) to create amorphous grain-boundary-free barriers; cobalt–ruthenium composite liner stacks; and ruthenium as a bulk metal fill replacing copper entirely at the most aggressively scaled nodes. A parallel thread covers ruthenium in RRAM/ReRAM crossbar arrays within BEOL metallization.
In this dataset, Applied Materials, Inc. is the most prolific assignee with at least 14 distinct patent documents in retrieved records, followed by TSMC with at least 9 documents and IBM with at least 7. The filing timeline reveals four maturity phases from foundational work in 2001–2007 through the advanced node and beyond-copper phase of 2022–2026, with over 35 US-jurisdiction documents in this dataset.
Patent Activity by Technology Cluster and Filing Phase
The dataset reveals four distinct technology clusters and four chronological maturity phases. Activity has accelerated sharply from 2022–2026, with TSMC and Applied Materials together accounting for the majority of the most recent filings in this dataset.
Patent Documents by Technology Cluster — Ruthenium Interconnect (Dataset Snapshot)
In this dataset, the Ru Liner/Cap Bilayer cluster accounts for the largest share of documents (~18), followed by Co–Ru Composite Liners (~10), Ru-Alloy Amorphous Barriers (~8), and Ru Bulk Metal Fill (~7), reflecting the liner/cap approach as the most actively developed integration strategy.
↗ Click bars to exploreFiling Activity by Maturity Phase — Ruthenium Interconnect (Dataset Snapshot)
In this dataset, filing volume increased substantially in each successive phase, with the Advanced Node phase (2022–2026) generating the highest concentration of documents (~28), reflecting accelerating commercial urgency around sub-3 nm BEOL integration.
↗ Click bars to exploreKey Application Areas for Ruthenium Barrier Layer Technology
Across the dataset, ruthenium barrier and liner technology is deployed across five principal application domains, ranging from advanced logic BEOL copper metallization at sub-5 nm nodes to stacked transistor device-level contacts, resistive memory integration, middle-of-line contacts, and gate stack applications.
Advanced Logic BEOL Sub-10 nm
The dominant application in the dataset is BEOL copper metallization in leading-edge logic. Applied Materials explicitly articulates the transition from cobalt liners (20 nm–3 nm node) to ruthenium liners at and below the 3 nm node. TSMC’s 2025 interconnect structure filings describe ruthenium-based liner layers with a bottom-to-sidewall thickness ratio of 2:1 to 8:1 in via openings for sub-5 nm dual damascene.
Advanced LogicStacked Transistor Nanosheet Contacts
As GAA nanosheet and stacked CFET architectures demand device-level interconnects with exceptional thermal stability, ruthenium and ruthenium aluminide (RuAl) are specifically targeted for source/drain vias. TSMC’s 2024–2025 filings address this directly, introducing RuAl as a thermally stable contact fill material for sequential 3D integration addressing the thermal budget requirements of CFET processes.
Device-Level ContactsResistive Memory RRAM/ReRAM BEOL
IBM exploits ruthenium as a hardmask protection layer for RRAM crossbar stacks embedded within BEOL ILD layers, where the ruthenium layer survives damascene process steps intact (IBM, 2020, US). TSMC’s parallel work focuses on ruthenium-based diffusion barriers in CBRAM structures to mitigate direct-shortcircuit leakage, with filings spanning 2023–2025.
Resistive MemoryMiddle-of-Line Contact Plugs
TSMC filings describe ruthenium-comprising contacts in MOL interconnect layers with air gap structures (TSMC, 2023, US), positioning ruthenium as an alternative to tungsten for contact plug applications. A separate TSMC filing on dual metal vias (2020, US) addresses contact resistance reduction through ruthenium integration in the MOL stack.
MOL IntegrationKey Patent Assignees in Ruthenium Interconnect Barriers — Retrieved Records Snapshot
In this dataset, Applied Materials, Inc. accounts for at least 14 patent documents in retrieved records, spanning every major ruthenium integration approach. TSMC contributes at least 9 documents in retrieved records concentrated in the 2022–2026 advanced node phase, reflecting the company’s role as primary manufacturing integrator.
Top Assignees by Filing Count — Ruthenium Interconnect Barrier (Dataset Snapshot)
↗ Click bars to exploreApplied Materials, Inc.
Applied Materials holds at least 14 patent documents in this dataset filed across US and WO jurisdictions from 2006 through September 2025, covering RuTa alloy barriers, Ru liner/cap bilayers for sub-3 nm nodes, Co–Ru composite liners (including 5 Å Ru + 20 Å Co ultra-thin stacks), Ta-doped Ru unified barrier-liner, Ru feature fill, and PVD ruthenium for gate stacks. Key filings include the 2006 seminal RuTa conductive barrier, the 2022–2023 Ru liner-and-cap family explicitly targeting the 3 nm node, and the 2025 sacrificial cobalt/ruthenium liner for copper reflow. Patent status ranges from granted US patents to pending WO applications filed as recently as 2025.
United StatesTaiwan Semiconductor Manufacturing Company
TSMC contributes at least 9 patent documents in this dataset filed in the US jurisdiction from 2020 through 2026, covering ruthenium oxide liners for low-resistance copper interconnects (2022–2023), metal nitride (RuNx/CoNx) intra-stack diffusion barriers (2022–2026), MOL contacts with air gap structures (2023), CBRAM diffusion barriers (2023–2025), and ruthenium-based liners for GAA/CFET stacked transistor device-level interconnects (2024–2025). The 2026 filing on metal nitride diffusion barrier formation (US) is the most recent document in the dataset. Patent status includes granted US patents and pending applications.
Taiwan — US FilingsForward-Looking Signals in Ruthenium Interconnect Patents (2024–2026)
The most recent filings (2024–2026) in this dataset signal at least five forward-looking trajectories, each addressing specific scaling or integration challenges that prior ruthenium liner generations did not fully resolve.
Ta-Doped Ru: Unified Barrier-Liner Replacing TaN/Ta/Ru Trilayers
Applied Materials’ 2024 filings describe forming a Ta-doped Ru layer by H₂/Ar plasma treatment of a TaN/Ru stack, creating a functionally graded film combining TaN’s diffusion barrier character with Ru’s low resistivity. This is positioned as a direct replacement for TaN/Ta/Ru trilayer stacks, reducing the total barrier cross-section while maintaining copper diffusion blocking. Both US and WO applications were filed in 2024.
Plasma-Cycle Ru Patterning: Enabling Subtractive Ru BEOL Metallization
Samsung’s 2024 US filing describes a multi-cycle N₂ passivation / H₂ reduction / O₂ etch approach to pattern ruthenium in a BEOL process, addressing the historically difficult etch challenge for Ru. This could unlock semi-damascene and subtractive Ru metallization at advanced nodes, bypassing conventional copper damascene fill entirely. The absence of other robust subtractive Ru patterning patents in this dataset signals an open competitive space.
Ruthenium vs. Ta/TaN: Barrier Layer Technology Dimensions
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| Dimension | Ruthenium (Ru) Barrier/Liner | Ta/TaN Conventional Barrier |
|---|---|---|
| Bulk Resistivity | ~7.6 μΩ·cm | Far higher (TaN ~200–500 μΩ·cm, Ta ~15–25 μΩ·cm) |
| Minimum Barrier Thickness | As thin as ~5 Å (0.5 nm) in latest Co/Ru stacks (Applied Materials, 2024) | Must exceed 4 nm to maintain adequate barrier and liner properties |
| Copper Wettability | Strong — enables direct electroplated Cu without separate PVD seed layer | Poor — requires separate PVD Cu seed layer for electroplating |
| Barrier Mechanism | Amorphous RuTa/RuTaN eliminates grain-boundary diffusion highways; RuNx blocks Co/Ru intermixing | TaN provides diffusion barrier; relies on minimizing grain boundaries via processing |
| Lattice Match to Cu | Ru(002)/Cu(111) lower lattice mismatch than Ta(110)/Cu(111) | Ta(110)/Cu(111) higher lattice mismatch; poorer epitaxial relationship |
| Patterning Maturity | Historically difficult to etch; Samsung 2024 plasma-cycle approach is an early solution | Well-established subtractive and damascene patterning processes |
| Technology Node Applicability | At and below 3 nm node (Applied Materials 2022–2024); stacked transistor/CFET (TSMC 2024–2025) | Effective to approximately 20 nm node before cross-section penalty becomes prohibitive |
| Metal Fill Capability | Ru thermal reflow enables void-free fill at aspect ratios ≥20:1 (Cypress, 2010; Tokyo Electron, 2017) | Not used as primary fill metal — serves only as liner/barrier |
Frequently Asked Questions: Ruthenium Interconnect Barrier Layer Technology
As interconnect half-pitch approaches 20 nm and below, the conventional TaN/Ta bilayer must exceed 4 nm to maintain adequate barrier properties, occupying a disproportionate fraction of the conductive cross-section. Ruthenium offers a bulk resistivity of approximately 7.6 μΩ·cm, strong copper wettability enabling direct electroplating without a PVD seed layer, and robust diffusion barrier character — while enabling far thinner barrier films than Ta/TaN allows at the same performance level.
The four sub-domains are: (1) pure ruthenium liners and caps used as conformal barrier/seed layers in dual damascene structures; (2) ruthenium alloyed with tantalum (RuTa) or doped with nitrogen (RuTaN) to create amorphous grain-boundary-free diffusion barriers; (3) cobalt–ruthenium composite liner stacks that decouple wetting, gapfill, and electromigration functions; and (4) ruthenium as a bulk metal fill replacing copper entirely at the most aggressively scaled nodes.
In this dataset, Applied Materials, Inc. (US) is the most prolific assignee, accounting for at least 14 distinct patent documents spanning US and WO jurisdictions from 2006 through September 2025. This breadth covers RuTa barrier layers, Ru liner/cap bilayers, Co–Ru composite liners, Ta-doped Ru barriers, Ru feature fill, and PVD ruthenium gate stacks.
Applied Materials’ 2024 filings describe forming a Ta-doped Ru layer by H₂/Ar plasma treatment of a TaN/Ru stack, creating a functionally graded film that combines TaN’s diffusion barrier character with Ru’s low resistivity. This is positioned as a direct replacement for TaN/Ta/Ru trilayer stacks, reducing total barrier cross-section. Both US and WO applications were filed in 2024.
Samsung’s 2024 US filing describes a multi-cycle N₂ passivation / H₂ reduction / O₂ etch approach to pattern ruthenium in a BEOL process. This addresses the historically difficult etch challenge for ruthenium and could unlock semi-damascene and subtractive Ru metallization at advanced nodes, bypassing conventional copper damascene fill. The dataset shows a lack of other robust subtractive Ru patterning patents, signaling an open competitive space.
Among retrieved results, the overwhelming majority of patents are filed in the US jurisdiction (over 35 documents), followed by WO/PCT (approximately 10 documents), SG (Singapore, approximately 3 documents, principally Lam Research), and EP (approximately 1 document, Intel). No significant filing activity in CN, KR, or JP jurisdictions is represented in this dataset.
Data and insights on this page are based on a limited patent and literature dataset and are for reference only. Figures may not represent the complete technology landscape.