SAQP achieves its pitch-quadrupling capability by performing two sequential self-aligned double patterning (SADP) operations on the same substrate. In each SADP step, conformal spacer material is deposited on patterned mandrel structures, the mandrel is selectively removed, and the remaining spacer features serve as the next-generation mandrel. By repeating this cycle twice, the final feature pitch is reduced to one-quarter of the original lithographic pitch — achieving 1/4 minimum pitch compared to the 1/2 minimum pitch of conventional SADP.

This process requires no change to the underlying photolithography exposure tool, making it directly compatible with existing ArF immersion scanner infrastructure. According to PatSnap patent data from Yangtze Memory Technologies (YMTC, 2018), this enables dramatic density increases in semiconductor integrated circuits without EUV capital expenditure.

Intel Corporation independently established the geometric underpinning of these techniques in a 2015 foundational patent, describing discrete structures with sidewalls defining oblique angles relative to the substrate surface. This angled-sidewall approach enables pitch reduction by generating features whose pitch is half that of the initial pattern after each spacer iteration, directly achieving quadruple-density patterning in a self-aligned manner. The oblique sidewall geometry is critical for enabling distinct region separation, which in turn allows each subsequent spacer pair to be individually addressable during etch.

Tokyo Electron Limited (TEL) contributed a significant variant employing a "staircase spacer" and reversal layer into the SAQP flow. As disclosed in TEL's 2021 patent, the process forms an initial pattern via X-Y double line exposures, applies a reverse material, and converts each initial trench pattern to a line through an etching step — achieving below-12nm lines and trenches with improved line edge roughness (LER) and line width roughness (LWR), producing self-aligned cross-pitch quad trenches. According to WIPO data, self-aligned patterning techniques represent one of the fastest-growing patent categories in semiconductor process technology.

SAQP doubles the pitch reduction of SADP by performing two sequential spacer-on-mandrel cycles, achieving 1/4-pitch resolution without modifying the ArF immersion lithography tool. This makes it the leading non-EUV route to sub-10nm fin pitch, as described by YMTC's 2018 patent and confirmed across the patent dataset.

Pitch walking is the primary yield-limiting mechanism in SAQP fin patterning. GLOBALFOUNDRIES' 2019 pitch walking solution demonstrates that LUT-based reticle pre-compensation using measured CD and SWA data at each intermediate step is an effective control strategy — shifting the control burden from expensive in-line metrology to a pre-computed design rule. The NIST metrology frameworks for semiconductor CD measurement underpin the measurement inputs that make this LUT approach viable.

Below-12nm line and trench patterning with improved LER/LWR is achievable using TEL's staircase-spacer SAQP variant, enabling cross-pitch quad trench formation applicable to both logic and memory layers. SAQP also extends to BEOL interconnect patterning in 3D NAND flash memory — not just FinFET front-end fins — as disclosed in YMTC's 2020 patent, enabling copper damascene metal line formation at 1/4-pitch without EUV exposure tools.

GLOBALFOUNDRIES research explicitly states that self-aligned multiple patterning enables semiconductor scaling before EUV reaches manufacturing maturity, and that line cut EPE at sub-30nm pitch is the next challenge requiring resolution. Explore the full patent landscape analytics for SAQP and related SAMP technologies on PatSnap.