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Run your analysis now →A patent landscape analysis of SiC MOSFET gate dielectric technology: filing trends, leading assignees, IPC composition and open claim space, based on 76 records filed 2015-2026.
Filing growth = 2021 (15 records) → 2024 (7); 2024 is the last year we treat as complete. Top-5 share = the 5 largest assignees ÷ all 76 records in scope (CR5), not the ranked leaders only.
This dataset tracks patent activity naming SiC MOSFET gate dielectric or gate insulation constructions, filtered to H01L29 and H10D30 classifications, across 76 published records filed between 2015 and the 2026 cut-off. The gate dielectric interface is the part of a SiC MOSFET most exposed to trapped charge and threshold-voltage drift, which is why so much of the filing activity in this space concentrates on layered insulation films, trap-charge engineering and channel mobility trade-offs rather than the wider device architecture.
Coverage runs from first filing in the window through the 2026-08-31 cut-off, with China, the United States, WIPO, Japan, the EPO and India as the receiving offices captured in the data.
Two views of the same 76 records: how filing activity has moved year over year, and which IPC subclasses the claims sit under.
Filings rose from 4 in 2017 to a peak of 15 in 2021, then fell to 7 by 2024 — a -53% change over that three-year span. 2025 and 2026 figures will rise as publications catch up; they should not yet be read as a continued decline.
Publication lags filing by roughly 18 months, so 2025 onwards are still filling in. Growth rates on this page therefore end at 2024; running them to the last bar would understate the field.
H01L accounts for 85.5% of the 76 records, with H10D covering 42.1% and the smaller H10P and H10W subclasses at 13.2% and 11.8% respectively. Since a record can carry several classes, these shares add up to more than 100% of the record total — they describe overlap, not a partition.
Shares are the percentage of the 76 records in scope. A patent can carry several IPC classes, so the shares add up to more than 100%.
This page is one run against one query. Ask Eureka your own question about sic mosfet gate dielectric patent landscape and every answer comes back with the patent numbers behind it.
Try EurekaThe filing addresses a coexistence problem in SiC-MOSFET power devices: high channel mobility and a high threshold voltage rarely hold together on a SiC substrate. Its answer is a layered gate insulation film with electric charge trap characteristics, engineered to produce an irregular threshold voltage along the channel length — with a deliberately shorter high-threshold region than the rest of the channel.This is one of the most-cited records in the dataset and illustrates the layered-trap-charge approach that recurs across the leading assignees' filings.


| # | Publication no. | Patent title | Citations |
|---|---|---|---|
| 1 | US20090173949A1 | Silicon carbide MOS field effect transistor with built-in schottky diode and method for manufacturing such tr… | 48 |
| 2 | CN113571584A | 一种SiC MOSFET器件及其制备方法 | 22 |
| 3 | WO2014010006A1 | Mos field effect transistor | 20 |
| 4 | US20150179744A1 | MOS field effect transistor | 18 |
| 5 | WO2012131898A1 | Silicon carbide semiconductor device | 18 |
| 6 | US20130234163A1 | Silicon carbide semiconductor device | 14 |
| 7 | WO2019124384A1 | Silicon carbide semiconductor device and power conversion device | 13 |
| 8 | US20150044840A1 | Method for producing silicon carbide semiconductor device | 13 |
| 9 | CN102339863A | 半导体装置 | 13 |
| 10 | WO2019123717A1 | Silicon carbide semiconductor device and power conversion device | 11 |
Citation counts favour older records in any searched corpus — treat them as a signal of influence on later filings, not a ranking of current relevance.
Patent titles are shown in the language they were filed in, not translated, so that each record stays verifiable against the original filing — a translated title will not match in Eureka or in any national register. Each row carries its publication number; clicking a row searches Eureka by that number.
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The five leading assignees hold 43.4% of all 76 records in scope, and the top 10 combined reach 61.8%. But the ranking runs to 46 companies, so more than half the field is a long tail of entrants with a handful of filings each — worth checking individually rather than assuming the leaders cover the space.
Filings climbed from 4 in 2017 to 15 in 2021 before dropping to 7 by 2024, a -53% change over that span. Because publication lags filing by roughly 18 months, 2025 and 2026 counts are still incomplete and should not be read as confirming a further slowdown.
China accounts for 43 of the tracked filings, well ahead of the United States at 12, WIPO/PCT at 7, Japan at 5, the EPO at 4 and India at 3. A gate-dielectric filing strategy aimed at manufacturing scale-up should treat the Chinese office as the primary competitive arena, not a secondary one.
H01L covers 85.5% of records and H10D 42.1%, with H10P and H10W each present in over a tenth of filings. Because records can carry multiple classes, this overlap signals that gate-dielectric claims routinely straddle general device structure and more specific sub-branches rather than sitting in one class alone.
Eureka can read the same corpus for gaps instead of for coverage: under-claimed branches adjacent to sic mosfet gate dielectric patent landscape, with the prior art for and against each one.
The dataset points to specific next steps depending on whether the goal is defensive clearance or a new filing.
With 46 companies in the ranking and only the top 10 covering 61.8% of records, a clearance search limited to the leaders will miss single-filing entrants holding narrow but live claims.
Explore assignee-level search in EurekaThe apparent drop from the 2021 peak is partly a publication-lag artefact; revisit the trend once 2025 filings finish appearing before concluding the field is shrinking.
Set up filing alerts in EurekaThe high co-occurrence between H01L and H10D suggests drafting strategies that straddle both — worth a claim-chart comparison before filing a new gate-dielectric application.
Build a claim comparison in EurekaThe dataset ranks 46 companies by filing count, with the leading assignee holding 8 records and the fifth-ranked holding 5. The top 5 assignees together account for 43.4% of all 76 records in scope, and the top 10 reach 61.8%. That leaves a long tail of smaller filers, many with only one or two records, so a leader-only view understates how fragmented ownership is beneath the top ranks.
Filings rose from 4 in 2017 to a peak of 15 in 2021, then fell to 7 by 2024 — a -53% change over that three-year window. Because patent publication typically lags filing by around 18 months, the 2025 and 2026 counts in this dataset are still incomplete and will rise as more applications publish. Treat 2024 as the last fully comparable year rather than reading the most recent years as a confirmed downturn.
China's receiving office accounts for 43 of the 76 tracked filings, by far the largest share, followed by the United States at 12 and WIPO/PCT filings at 7. Japan, the EPO and India each see single-digit counts (5, 4 and 3 respectively). This distribution points to China as the primary jurisdiction to monitor for both competitive filings and freedom-to-operate risk in this technology.
US20150179744A1, assigned to Hitachi and filed in 2015, claims a SiC MOSFET with a layered gate insulation film exhibiting electric charge trap characteristics, producing an irregular threshold voltage along the channel length with a shorter high-threshold region. It is one of the most-cited records in this dataset, indicating it has shaped later filings' claim language around trap-charge engineering. Anyone designing a similar layered, trap-engineered gate insulation approach should review its specific claims closely rather than assume the general concept is free to use.
IPC composition shows heavy concentration in H01L (85.5% of the 76 records) and H10D (42.1%), with H10P and H10W each appearing in roughly a tenth of records. The smaller presence of H10P and H10W relative to H01L and H10D suggests these adjacent branches carry less claim density, making them a reasonable starting point for novelty searches. Combined with the long tail of single-filing assignees, this points to specific sub-branches within gate dielectric engineering that are not yet dominated by any one player.
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Disclaimer. This page is generated from Patsnap Eureka data drawn from a limited snapshot of global patent and scientific-literature records, and is provided for general information and reference only.
Patent data carries inherent limitations: recent filings (typically the most recent 18–24 months) are under-counted due to standard publication lag; counts may be reported at either a patent-family or a patent-record basis and are not always directly comparable; classification, applicant-name, and citation data may contain errors, duplicates, or omissions; and the underlying search query defines and constrains the scope shown. As a result, the analysis may be incomplete or inaccurate and may not reflect the full technology landscape.
Nothing on this page constitutes an exhaustive prior-art, novelty, freedom-to-operate, or validity search, nor does it constitute legal, financial, investment, or professional advice, and it should not be relied upon as such. Any patent, commercial, or strategic decision should be verified independently and reviewed with qualified patent, legal, and domain professionals. Patsnap makes no warranties, express or implied, as to the accuracy, completeness, or fitness for any particular purpose of the information presented.
Machine translation. Assignee and organisation names originally recorded in Chinese, Japanese or Korean have been rendered into English by an AI translation step so that the tables stay readable. These renderings are best-effort and may not match a company's registered English name; the original name is what the underlying patent record carries, and it is what any Eureka query launched from this page uses.