SiC Substrate Defect Density & Yield — PatSnap Eureka
SiC Substrate Defect Density and Power Device Yield in 150mm Wafer Production
Micropipes, basal plane dislocations, carbon inclusions, and stacking faults are the primary gating factors for SiC power device yield. At 20 defects/cm², a 50A-class die achieves approximately 1% yield — making defect reduction the single largest lever for cost reduction in 150mm production.
SiC Die Yield vs. Die Size at 20 Defects/cm²
Cree Inc. production data: yield collapses sharply as die area increases at a fixed defect density of 20/cm².
Four Defect Classes That Govern SiC Power Device Yield
SiC crystal growth above 2000°C by physical vapor transport sublimation creates a spectrum of crystallographic defects that propagate from boule to substrate to epitaxial layer to finished device. Understanding each kill mechanism is the foundation of yield engineering.
Micropipes & Large-Pit Defects
A micropipe is a super-screw dislocation with a hollow core that propagates through the entire wafer thickness. Any active device region containing one exhibits catastrophic leakage or breakdown failure. Large pit defects and triangular defects caused by substrate carbon inclusions are explicitly classified as component killer defects by Showa Denko's 2019 SiC epitaxy wafer patent. Controlling carbon inclusion density to 0.1–2.5/cm² is required to keep large-pit and triangular defect density in the epitaxial layer at ≤0.6/cm².
≤0.6 defects/cm² epi thresholdBasal Plane Dislocations (BPDs)
BPDs cause forward-voltage drift in bipolar devices during operation. When minority carriers are injected into a drift layer containing BPDs, recombination energy drives dislocation glide and expansion into triangular stacking faults, progressively increasing on-resistance and forward voltage drop. DC stress drives degradation faster than pulsed stress because continuous carrier injection causes persistent recombination-enhanced dislocation motion and simultaneous Joule heating. Patent landscape analytics from DENSO show BPD density can predict post-manufacture electrical drift before fabrication begins.
KOH-etch BPD limit: <550/cm²BPD-Sourced Stacking Faults
Stacking faults propagating from BPDs are detectable at the wafer level before metallization. Fuji Electric's 2022 patent demonstrates that irradiating an SiC-MOSFET wafer at the interlayer insulation film stage with light accelerates stacking fault growth to its maximum possible extent before any electrical or thermal in-spec stress is applied. Photoluminescence scanning then detects the resulting faults before source/drain electrode formation—eliminating devices with latent BPD-sourced stacking faults before costly back-end processing.
Pre-metallization PL screeningCarbon Inclusions in Epitaxial Growth
Carbon inclusions in the SiC substrate act as nucleation sites for large-pit and triangular defects in the epitaxial layer. These defects are classified as component killers because they appear within active device regions and cause immediate electrical failure. The quantitative link between substrate carbon inclusion density (0.1–2.5/cm²) and epitaxial defect density (≤0.6/cm²) established by Showa Denko provides a direct specification target for substrate procurement and epitaxial process control in advanced materials manufacturing.
0.1–2.5 inclusions/cm² substrateDefect Density Thresholds That Define SiC Economics
The relationship between substrate defect density and die yield is approximately governed by a Poisson kill model: yield decreases exponentially with increasing defect density and die area. For SiC, this relationship is severely nonlinear due to the very high density of native defects compared to silicon. WIPO patent data confirms this is a global challenge—not a single-vendor problem.
Cree Inc.'s production data, cited in their Large-area SiC device and manufacturing method patent, provides the most widely-referenced quantitative baseline: at a combined defect density of 20 cm⁻², a 2mm × 2mm die achieves approximately 50% yield, a 33mm × 33mm die yields less than 20%, and a die dimensioned for 50A current handling falls to approximately 1% yield. These figures explain why large-area SiC power switches demanded by motor drive applications were historically impractical as single-die solutions on early-generation substrates.
Cree's solution was selective interconnection: multiple smaller, electrically tested, defect-free SiC die are identified on the wafer and then selectively wire-bonded or contact-connected to form the equivalent of a large-area device. This approach transforms the yield problem from a single-die yield calculation into a probability calculation over smaller unit cells.
GlobalWafers' 2025 SiC wafer patent specifies BPD density thresholds directly: both seed-end and crown-end surfaces of a 150mm-class SiC boule should exhibit KOH-etch BPD densities below 550 pieces/cm², with photoluminescence-detected BPD density below 2000 pieces/cm². The difference ratio between seed-end and crown-end BPD density is limited to 26% or less (typically 10–20%), ensuring axially uniform substrate quality across the boule and thus consistent yield lot-to-lot. These specifications are now referenced in SiC supply chain quality gates across the industry.
Resonac Corporation's 2025 filings quantify a novel non-MP defect class—distinguishable from micropipes by KOH etch pit morphology—whose acceptable density range in a 150mm substrate is 0.1 to 50 pieces/cm². Substrates containing this non-MP defect class in controlled concentrations exhibit reduced SORI change after ion implantation, which translates directly to improved lithographic alignment accuracy and thus higher yield through the device fabrication flow. The European Patent Office has granted key Resonac filings in this area, reflecting the international significance of these specifications.
Quantitative Defect Thresholds Across the SiC Supply Chain
Key defect density specifications from leading patent filings, mapped across defect class, measurement method, and assignee — all traceable to primary patent sources.
SiC Substrate Defect Density Thresholds by Class
Maximum acceptable defect densities (pieces/cm²) as specified in leading patent filings. Carbon inclusion and large-pit thresholds are the tightest constraints on epitaxial yield.
BPD Axial Uniformity Requirement — 150mm SiC Boule
GlobalWafers (2025) limits the difference ratio between seed-end and crown-end KOH-etch BPD density to ≤26%, with typical production achieving 10–20% variation.
SiC Substrate Stress Limits for High-Yield Device Manufacturing (Huawei, 2024)
Internal stress within a SiC substrate must be controlled across measurement points distributed 1μm to 250μm from the first surface. Exceeding these limits causes wafer bow during epitaxial deposition and patterning failures across the 150mm field.
How Leading SiC Producers Engineer Defects Out of 150mm Substrates
Five distinct engineering strategies address defect density before device fabrication begins — each targeting a different mechanism in the defect propagation chain.
| Strategy | Key Specification | Assignee / Date | Yield Impact |
|---|---|---|---|
| Dopant uniformity & resistivity control | Dopant concentration within ±15% center to within 1mm of edge; 2×10¹⁸ to 6×10¹⁹ /cm³; resistivity spread ≤2 mΩ·cm | Resonac (2023) | Reduces device-to-device characteristic variation; eliminates edge-die resistivity outliers from facet-region high-nitrogen zones |
| Composite substrate with defect-partitioned layers | High-defect-density base substrate bonded to low-defect-density SiC active layer; active layer exhibits lower BPD, mixed dislocation, stacking fault, and point defect density than base | Sumitomo Electric (2012) | Screens active device zone from defects propagating from bulk substrate; directly reduces density of electrically active killer defects during epitaxial growth |
| Internal stress reduction & uniformity | Stress differential ≤35 MPa; absolute stress ≤30 MPa at any measurement point 1μm–250μm from first surface | Huawei (2024) | Reduces SORI, wafer bow during epitaxial deposition, and photolithography depth-of-focus margin loss across 150mm field |
| Gradient-doped epitaxial buffer layers | Gradient-doped buffer layer structure in epitaxial stack relieves lattice mismatch and stress between substrate and device active layer | Shenzhen Zhengyan Microelectronics (2025) | Improves device reliability, stability, and fabrication yield by reducing defect nucleation at substrate-to-epi interface |
| Thin-substrate lift-off for substrate reuse | Semi-insulating SiC single crystal growth substrate with lift-off for reuse; substrate accounts for 60% of total device manufacturing cost and ~50% of device on-resistance | Shandong University (2024) | Reduces substrate-induced wafer bow and epitaxial layer stress simultaneously; co-optimises cost reduction and defect density reduction |
Compare SiC Substrate Engineering Patents Side-by-Side
PatSnap Eureka lets you extract and compare specification tables from 60+ SiC patent documents in seconds — no manual reading required.
Defect Inspection Methods That Protect Yield Before Value-Add Processing
Yield loss from substrate defects is only recoverable if defects are identified before costly processing is performed. Five inspection modalities are established across the patent dataset.
Photoluminescence (PL) Scanning
The dominant in-line method for SiC stacking fault detection. Fuji Electric Advanced Technology's 2004 foundational patent establishes that irradiating an SiC pn-junction wafer with above-bandgap laser light causes stacking faults to emit characteristic luminescence distinguishable from defect-free regions. Fuji Electric's 2022 manufacturing method advances this by accelerating stacking fault growth via light exposure before PL scanning — eliminating devices with latent BPD-sourced stacking faults before source/drain electrode formation and saving back-end processing cost. Patent analytics confirm PL scanning is the most-cited inspection method across SiC device patents.
KOH Etch Pit Analysis
The standard destructive method for BPD and micropipe density quantification. Showa Denko's 2023 CN patent addresses measurement equipment calibration: a standard sample composed of material whose emission intensity does not change under repeated excitation light exposure is used to measure the signal-to-noise ratio before each wafer measurement session. This procedural control ensures apparent changes in defect density readings are not artifacts of equipment drift — a critical requirement for statistical process control in 150mm production where lot-to-lot defect density comparisons drive substrate acceptance decisions. Standards bodies including NIST reference KOH etch pit density as a fundamental SiC characterisation method.
Key Players Driving SiC Substrate Defect Management
Analysis of approximately 60 patent documents identifies six dominant assignees with distinct technical strategies for defect density control in 150mm SiC power device production.
Resonac Corporation / Showa Denko
Patents covering 8-inch n-type SiC substrate dopant uniformity (±15% specification); non-MP defect classification and density control for SORI management (0.1–50/cm²); SiC substrate and ingot resistivity uniformity for laser processing yield (≤2 mΩ·cm spread); and the SiC epitaxial wafer carbon inclusion control standard (0.1–2.5/cm²). Resonac's portfolio reflects a systematic strategy of defining quantitative defect density specifications that directly map to device yield and processing yield outcomes on 6-inch and 8-inch platforms. Their 2025 filings explicitly address diameter scaling from 150mm to 200mm.
6-inch & 8-inch quantitative specsSumitomo Electric Industries
Focuses on composite substrate architectures and stacking fault suppression during high-temperature processing. Their patents on SiC substrates with partitioned defect density layers establish that the active layer's defect density is explicitly lower than the base substrate's defect density as a design requirement — validating that the defect density hierarchy between base and active layers is intentional and yield-driven. Foundational to multi-layer SiC substrate design philosophy across the industry.
Defect-partitioned layer architectureCree Inc.
Pioneered the quantitative relationship between micropipe/dislocation defect density and large-die yield, and the selective-die-interconnection approach to circumventing yield limits on early-generation substrates. Their 2007 patent provides the foundational data showing that at 20/cm² defect density, a 50A-class die achieves ~1% yield. Their bipolar semiconductor device degradation minimization patent establishes the geometric solution to BPD-sourced stacking fault yield loss by positioning fault propagation planes away from device active regions.
Selective die interconnection methodDENSO Corporation
Advanced the concept of substrate-level BPD density as an input variable to manufacturing control decisions. Their 2025 patent on SiC semiconductor device manufacturing with BPD-based electrical characteristic prediction represents state-of-the-art integration of substrate metrology data into process flow gate decisions: BPD density is measured, a predictive model estimates electrical characteristic drift (current-on variation) during device operation, and only substrates below a BPD threshold are cleared for continued fabrication — directly linking measured defect density to predicted field-reliability metrics.
BPD-to-field-reliability prediction loopFuji Electric
Focuses on in-line wafer-level inspection methodology, particularly PL-based stacking fault screening as a mid-process yield filter. Their 2022 manufacturing and inspection method demonstrates that accelerated stacking-fault growth by light exposure followed by PL scanning identifies latent defects at the mid-process stage — saving back-end processing cost on dies that would fail in the field. Their 2004 foundational patent established PL scanning as the primary in-line method for SiC stacking fault detection.
Pre-metallization PL screeningGlobalWafers
Emerging as a significant player with quantitative BPD density specifications across the boule axis in their 2025 CN patent: KOH-etch BPD density below 550/cm² at both seed and crown ends, PL-BPD density below 2000/cm², and axial uniformity ratio ≤26%. These specifications reflect increasing vertical integration ambitions in SiC substrate supply. Alongside Resonac, GlobalWafers is one of the few companies specifying axial uniformity as a supply chain quality gate for 150mm substrate procurement. PatSnap's platform tracks their filing velocity in real time.
Axial boule uniformity specsHow 150mm to 200mm Scaling Compounds Defect Density Challenges
A clear trend across all major players is the transition from 150mm to 200mm diameter substrates. Resonac's 8-inch SiC substrate patents (EP 2023) and their 2025 JP pending filing explicitly cite diameter scaling from 6 to 8 inches as an energy-saving efficiency driver — acknowledging that defect density control becomes more challenging with increasing wafer area.
New non-MP defect classes must be managed to maintain acceptable yield at 200mm. Resonac's 2025 filings confirm that edge resistivity non-uniformity from facet regions, dopant concentration gradients, and novel non-MP defect morphologies all become more difficult to control at larger diameters — requiring tighter specification management than 150mm production. The Semiconductor Industry Association has identified 200mm SiC as a critical capacity milestone for the power electronics industry.
The substrate cost problem also intensifies at 200mm. Shandong University's 2024 patent notes that the SiC substrate accounts for 60% of total device manufacturing cost, and its electrical resistance accounts for approximately half of device on-resistance. Substrate lift-off for reuse — reducing substrate-induced wafer bow and epitaxial layer stress simultaneously — emerges as a co-optimised cost and defect reduction strategy for the 200mm transition. PatSnap's API enables automated tracking of 200mm SiC patent filings as this transition accelerates.
Chinese entities including DENSO's Chinese subsidiary, Shandong University, Nanjing University of Information Science, the China Electronic Product Reliability and Environmental Testing Institute, and Huawei collectively reflect the rapid escalation of Chinese R&D investment in SiC substrate quality control, bipolar degradation characterisation, and low-cost substrate engineering — particularly for the 150mm production node as a stepping stone to 200mm capability.
SiC Substrate Defect Density & Power Device Yield — Key Questions Answered
Micropipes and large-pit defects are the most severe killer defects for power device fabrication. A micropipe is a super-screw dislocation with a hollow core that propagates through the entire wafer thickness; any active device region containing one will exhibit catastrophic leakage or breakdown failure. Large pit defects and triangular defects caused by substrate carbon inclusions are explicitly classified as component killer defects.
Controlling the substrate carbon inclusion density to between 0.1 and 2.5 inclusions/cm² enables reduction of the total density of large pit defects and triangular defects in the epitaxial layer to 0.6 defects/cm² or less—a quantitative threshold directly tied to acceptable device kill rates, as established by Showa Denko's 2019 SiC epitaxy wafer manufacturing process patent.
Basal plane dislocations cause forward-voltage drift in bipolar devices during operation. When minority carriers are injected into a drift layer containing BPDs, recombination energy drives dislocation glide and expansion into triangular stacking faults, progressively increasing on-resistance and forward voltage drop. DENSO's 2025 patent demonstrates that BPD density can be measured prior to device fabrication and used to predict post-manufacture electrical drift, enabling substrate-level reject decisions that prevent wasted downstream processing.
At a combined defect density of 20 cm⁻², a die dimensioned for 50A current handling falls to approximately 1% yield, as demonstrated by Cree Inc.'s production data cited in their Large-area SiC device and manufacturing method patent (2007). This makes defect reduction the single largest lever for cost reduction in SiC power device manufacturing.
GlobalWafers' 2025 SiC wafer patent specifies that both seed-end and crown-end surfaces of a 150mm-class SiC boule should exhibit KOH-etch BPD densities below 550 pieces/cm², with photoluminescence-detected BPD density below 2000 pieces/cm². The difference ratio between seed-end and crown-end BPD density is limited to 26% or less (typically 10–20%), ensuring axially uniform substrate quality across the boule and thus consistent yield lot-to-lot.
Huawei's 2024 SiC substrate patent establishes that internal stress within a SiC substrate must be controlled to a stress differential of ≤35 MPa and absolute stress ≤30 MPa at any given measurement point. The patent explicitly states that applying a SiC substrate with lower stress and more uniform stress distribution to semiconductor device manufacturing increases device yield.
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References
- Manufacturing process for a SiC epitaxy wafer — Showa Denko K.K., 2019
- Bipolar degradation screening method, apparatus and system for SiC devices — China Electronic Product Reliability and Environmental Testing Institute, 2025
- SiC semiconductor device manufacturing method (BPD-based prediction) — DENSO Corporation, 2025
- Large-area SiC device and manufacturing method — Cree Inc., 2007
- SiC single crystal substrate (non-MP defect, SORI control, TW) — Resonac Corporation, 2025
- SiC single crystal substrate (non-MP defect, CN) — Resonac Corporation, 2023
- SiC wafer and forming method (BPD density thresholds) — GlobalWafers Co., Ltd., 2025
- n-type SiC single crystal substrate (dopant uniformity, 8-inch) — Resonac Corporation, 2023
- 8-inch n-type SiC single crystal substrate (EP) — Resonac Corporation, 2023
- SiC substrate, semiconductor device and method for manufacturing SiC substrate (composite structure) — Sumitomo Electric Industries, 2012
- Semiconductor device (JFET, defect-partitioned SiC substrate) — Sumitomo Electric Industries, 2012
- SiC substrate (stress distribution, semiconductor device yield) — Huawei Technologies, 2024
- Manufacturing method for SiC semiconductor device / inspection method — Fuji Electric, 2022
- Inspecting method and apparatus for SiC semiconductor device — Fuji Electric Advanced Technology, 2004
- SiC wafer defect measurement method, standard sample, and SiC epitaxial wafer manufacturing method — Showa Denko, 2023
- SiC single crystal substrate / SiC epitaxial wafer (Resonac, JP pending) — Resonac Corporation, 2025
- Monitoring method during SiC wafer processing — Shanghai Jita Semiconductor, 2025
- Semiconductor device inspection apparatus — Toshiba, 2019
- SiC power device and manufacturing method — Shenzhen Zhengyan Microelectronics, 2025
- SiC power device and manufacturing method — Shandong University, 2024
- SiC substrate and SiC ingot (resistivity uniformity) — Resonac Corporation, 2022
- World Intellectual Property Organization (WIPO) — International Patent Database
- European Patent Office (EPO) — SiC Substrate Patent Registry
- National Institute of Standards and Technology (NIST) — SiC Characterisation Methods
- Semiconductor Industry Association — 200mm SiC Capacity Roadmap
All data and statistics on this page are sourced from the references above and from PatSnap's proprietary innovation intelligence platform. Patent document analysis conducted via PatSnap Eureka across approximately 60 SiC substrate and power device patent documents.
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