SiC Superjunction MOSFET Technology Landscape 2026
SiC Superjunction MOSFET Technology Landscape 2026
SiC superjunction MOSFETs apply charge-balance pillar columns to break the one-dimensional Baliga limit on the Ron,sp–BV trade-off. Simulation results show 27–40% BFOM improvements over conventional SiC MOSFETs across 650 V to 3.3 kV ratings.
Breaking the SiC Baliga Limit with Superjunction Architecture
Silicon carbide superjunction MOSFETs exploit alternating n-type and p-type pillar columns in the drift region to enable two-dimensional charge compensation. In the off-state, these pillars fully deplete one another to form a near-rectangular electric field profile, dramatically increasing breakdown voltage. In the on-state, current flows through the highly doped n-column, yielding lower on-resistance than a conventional drift layer at the same BV.
The central innovation challenge is that SiC’s small impurity diffusion coefficient, chemical hardness, and high critical electric field make it significantly harder to fabricate precision pillar structures compared to silicon. Process methods including multi-epitaxial deposition, channeled ion implantation, and trench-fill approaches are the critical manufacturing bottlenecks identified across retrieved records spanning 2017–2026.
Core technical sub-domains in this dataset include vertical pillar architecture variants (planar SJ-DMOS, trench SJ-UMOS, floating/partial SJ), integrated diode structures to suppress parasitic body-diode effects, edge termination and junction isolation for high-voltage reliability, and process enablement methods. The SJ UMOS FET achieves at least 31% reduction in the Ron,sp × QG,sp figure of merit compared to SJ DMOS over 0.6–10 kV ratings.
In retrieved records, General Electric Company is the most prolific single assignee with 5 records across WO, US, and EP jurisdictions, while NAMI MOS CO., LTD. leads cell-level structural innovation with US-granted patents. Chinese assignees including Suzhou Kaiwit Semiconductor Co., Ltd. are filing at increasing velocity in the CN jurisdiction, signalling a transition from academic simulation to IP-protected device concepts in this dataset.
Structural Clusters and Filing Trends in SiC SJ MOSFET Innovation
Retrieved records reveal four distinct technology clusters driving SiC superjunction MOSFET innovation: vertical pillar architectures, floating/partial SJ structures, integrated diode designs, and edge termination process methods. Filing activity in this dataset spans 2017–2026, with density shifting from US/JP incumbents toward Chinese fabless assignees from 2024 onwards.
SiC SJ MOSFET Records by Technology Cluster (Dataset Snapshot)
In this dataset, edge termination and vertical pillar architecture clusters each account for the largest share of identifiable patent records, led by General Electric and NAMI MOS respectively.
↗ Click bars to exploreSiC SJ MOSFET Activity by Filing Period — Dataset Snapshot
In this dataset, filing and publication activity concentrated in 2021–2023 for academic simulation studies, with a distinct patent filing surge from Chinese assignees visible in the 2024–2026 period.
↗ Click bars to exploreKey Application Domains for SiC Superjunction MOSFETs
Retrieved records identify four primary application domains driving SiC superjunction MOSFET development: EV traction inverters, photovoltaic and energy storage converters, industrial power conversion and grid infrastructure, and pulsed power switching — each placing distinct demands on voltage rating, switching loss, and ruggedness.
EV Traction Inverters
Multiple Chinese patent filings, including three active CN patents from Suzhou Kaiwit Semiconductor Co., Ltd. filed in early 2026, explicitly cite new-energy vehicle traction inverters as the primary target market. The combination of high breakdown voltage (1.2–3.3 kV range), low on-resistance, and high switching frequency directly reduces inverter heat sink requirements and increases power density. A 2022 literature review on SiC mass commercialization confirms EV traction as the dominant commercial pull factor for SiC SJ devices.
Power ElectronicsPhotovoltaic and Energy Storage
The 650 V–1,700 V voltage range and efficiency focus for SiC SJ MOSFETs appear in photovoltaic inverter and energy storage contexts cited in Chinese patent background sections. Reduced switching loss relative to conventional SiC MOSFETs is the critical metric for these high-cycle-count applications. A 2022 literature review on silicon carbide processing for power MOSFETs covers this application context in detail.
Renewable EnergyIndustrial Power and Grid
Industrial drives, smart grid equipment, and rail traction converters are cited in multiple filings as target segments for 3.3 kV+ SiC SJ devices. Mitsubishi Electric’s 2024 DE-jurisdiction pending patent on a SiC semiconductor device with SJ structure addresses precision low-resistance column contacts required for high-voltage grid-scale equipment. Fuji Electric’s 2025 EP inverter circuit patent explicitly addresses saturation current control for inverter operation targeting industrial markets.
Industrial ConversionPulsed Power High-Voltage Switching
A 2021 literature study introduced SJ structure into 4H-SiC drift step recovery diodes (DSRDs) for pulsed power applications, achieving 28% higher breakdown voltage and 31% higher dV/dt output compared to conventional SiC DSRDs. This extends the SJ architecture beyond inverter domains into non-inverter high-voltage switching applications. The result demonstrates that charge-balance pillar design translates to improved pulsed performance metrics in hard-recovery diode contexts.
Pulsed PowerKey Patent Assignees in SiC Superjunction MOSFETs (Retrieved Records)
In this dataset, General Electric Company and NAMI MOS CO., LTD. each account for the highest record counts among named assignees in retrieved records, with GE concentrating on edge termination IP and NAMI MOS on cell-level structural innovation. Japanese incumbents Fuji Electric and Toshiba hold positions across both cell and device-level IP, while Chinese assignees are filing at accelerating velocity primarily in the CN jurisdiction.
Top Assignees by SiC SJ MOSFET Record Count in Retrieved Records (Dataset Snapshot)
↗ Click bars to exploreGeneral Electric Company
General Electric holds 5 records across WO (2017), EP (2018), and multiple US grants (2019–2022) in this dataset, making it the most prolific single SiC SJ-specific assignee in retrieved records. Its patent strategy focuses on a coordinated multi-jurisdiction family covering edge termination designs with graded-doping implanted regions of second conductivity type for SiC SJ power devices, plus fast-switching super-junction power device IP. These active patents represent a high-priority freedom-to-operate concern for any company commercializing SiC SJ devices globally.
United StatesNAMI MOS CO., LTD.
NAMI MOS holds 5 records in this dataset across active and pending US patents filed 2022–2025, covering SiC SJ trench MOSFET cell architecture (2022), shielded gate trench SJ MOSFET with multi-stepped epitaxial structure (2024), saturation current pinching SJ MOSFET with buried P-shield regions (2025), and a planar MOSFET with JBS diode integration (2025). This dense cluster of cell-level structural IP positions NAMI MOS as the most active US-jurisdiction filer targeting the 650 V–1,200 V segment in retrieved records. Competitors should monitor this family closely for freedom-to-operate exposure.
United StatesFive Convergent Directions in SiC SJ MOSFET Innovation (2024–2026)
The most recent filings and publications in this dataset (2024–2026) point to five convergent directions: saturation current pinching for short-circuit ruggedness, JBS/Schottky diode integration, shielded gate trench architectures, high-volume Chinese fabless IP at 3.3 kV+ nodes, and Mitsubishi Electric’s SJ column contact optimization.
Saturation Current Pinching for Short-Circuit Ruggedness
NAMI MOS’s 2025 US pending application introduces buried P-shield (BPS) regions with a saturation current pinching (SCP) structure in the JFET region, explicitly targeting short-circuit capability as a first-class design criterion alongside on-resistance. Short-circuit withstand time (tsc) is a persistent weakness of SJ structures compared to conventional SiC MOSFETs due to higher peak currents during fault conditions. Innovations targeting tsc — including floating p-regions and BPS structures — represent high-value differentiators for automotive and safety-critical industrial applications.
JBS and Schottky Diode Integration into SJ Cell
Multiple 2024–2026 filings integrate Junction Barrier Schottky (JBS) diodes within the SJ cell to eliminate parasitic body diode turn-on and reduce reverse conduction losses. Body diode reverse recovery is a critical reliability concern in SiC — bipolar degradation from basal plane dislocations causes forward voltage drift over device lifetime. Retrieved simulation studies report reverse recovery charge (Qrr) reductions of 43–84% for MOS-channel diode embedded SJ-MOSFET structures, a direction visible in NAMI MOS’s 2025 planar MOSFET patent and Chinese fab designs.
SiC Superjunction MOSFET vs. Conventional 4H-SiC Vertical MOSFET
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| Dimension | SiC Superjunction MOSFET | Conventional 4H-SiC Vertical MOSFET |
|---|---|---|
| Ron,sp–BV Trade-off | Breaks 1D Baliga limit via 2D charge compensation in n/p pillar columns | Constrained by 1D Baliga limit; Ron,sp scales steeply with BV |
| BFOM Improvement (Simulation) | 27–40% higher BFOM over conventional vertical MOSFETs at comparable voltage ratings (retrieved records) | Baseline reference; no pillar charge compensation |
| Electric Field Profile | Near-rectangular profile in off-state due to full pillar depletion; higher BV | Triangular field profile; peak field at junction limits BV |
| Critical Breakdown Field (Effective)”> | Approximately 30% lower effective critical field due to longer ionization paths in SJ structure | Standard 4H-SiC critical field; well-characterised termination designs |
| Short-Circuit Ruggedness (tsc) | Persistent weakness; higher peak currents during fault; mitigated by floating p-regions and BPS structures | Generally superior tsc compared to SJ equivalents at same voltage rating |
| Body Diode / Reverse Recovery | Parasitic body PIN diode present; integrated JBS/MOS-channel diode structures reduce Qrr by 43–84% (simulation) | Parasitic body diode with bipolar degradation risk from basal plane dislocations |
| Fabrication Complexity | High; deep narrow pillar formation requires multi-epi deposition, channeled implantation, or trench-fill; no commercial SJ SiC product confirmed in this dataset | Established manufacturing process; commercially available at 650 V–3.3 kV |
| Gate Configuration Variants”> | Planar (SJ-DMOS) and trench (SJ-UMOS); SJ UMOS achieves ≥31% lower Ron,sp × QG,sp vs SJ DMOS | Planar and trench (UMOS) gate configurations commercially available |
Frequently Asked Questions: SiC Superjunction MOSFET Technology
The Baliga Figure of Merit (BFOM = BV²/Ron,sp) is the central performance benchmark for power MOSFETs, measuring the trade-off between breakdown voltage and specific on-resistance. SiC superjunction structures use alternating n/p pillar columns in the drift region to enable two-dimensional charge compensation, enabling a near-rectangular electric field profile in the off-state. Retrieved simulation studies report 27–40% BFOM improvements for SiC SJ structures over conventional vertical MOSFETs at comparable voltage ratings from 650 V to 3.3 kV.
SiC’s small impurity diffusion coefficient, chemical hardness, and high critical electric field make it significantly harder to form precision pillar structures compared to silicon. Process methods required include multi-epitaxial deposition, channeled ion implantation, and trench-fill approaches. The absence of commercially demonstrated SiC SJ products in this dataset confirms that deep, narrow, charge-balanced pillar formation in SiC remains an unsolved manufacturing challenge.
Short-circuit withstand time (tsc) is a persistent weakness of SJ structures compared to conventional SiC MOSFETs, due to higher peak currents during fault conditions. Retrieved literature and patents address this through floating p-regions (which deplete the p-pillar, p-shield, and floating p-regions under fault to limit current), and buried P-shield (BPS) structures with saturation current pinching (SCP) in the JFET region, as seen in NAMI MOS’s 2025 US pending application.
In this dataset, General Electric Company is the most prolific single assignee with 5 records across WO, US, and EP jurisdictions focusing on edge termination IP (2017–2022). NAMI MOS CO., LTD. holds 5 records with active US patents covering SJ trench MOSFET, shielded gate trench, and saturation current pinching structures (2022–2025). Suzhou Kaiwit Semiconductor Co., Ltd. has 4 active CN patents filed in early 2026. Fuji Electric Co., Ltd. holds 3 records including a US grant from December 2024.
Body diode reverse recovery is a critical reliability concern in SiC because bipolar degradation from basal plane dislocations causes forward voltage drift over device lifetime. Integrating Schottky barrier diodes (SBD), Junction Barrier Schottky (JBS) diodes, or MOS-channel diodes directly into the SJ-MOSFET cell suppresses parasitic body PIN diode turn-on. Retrieved simulation studies in this dataset report reverse recovery charge (Qrr) reductions of 43–84% and significant improvements in the Ron,sp × Cgd figure of merit for these integrated structures.
General Electric holds a coordinated multi-jurisdiction patent family covering graded-doping termination regions with implanted regions of second conductivity type for SiC SJ power devices, spanning WO (2017), EP (2018), and multiple US grants (2019–2022). In 4H-SiC SJ devices, the effective critical breakdown field is approximately 30% lower than in conventional devices due to longer ionization paths, making differentiated termination design essential. This active family is described in the dataset as a high-priority freedom-to-operate concern for any company commercializing SiC SJ devices globally.
Data and insights on this page are based on a limited patent and literature dataset and are for reference only. Figures may not represent the complete technology landscape.