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SiC vs GaN EMC Conducted Emissions — PatSnap Eureka

SiC vs GaN EMC Conducted Emissions — PatSnap Eureka
EMC Design · Wide-Bandgap Power Electronics

SiC vs. GaN Inverter EMC: Conducted Emissions Design Compared

SiC and GaN wide-bandgap inverters share a common EMC challenge but demand fundamentally different design strategies — from noise spectrum and parasitic management to filter architecture and gate-drive control. This analysis draws on 50+ patent and literature sources from ETH Zurich, Virginia Tech, Oak Ridge National Laboratory, and more.

Conducted Emission Frequency Range: SiC 150 kHz–30 MHz vs. GaN 150 kHz–400 MHz Horizontal bar comparison showing that SiC inverters produce conducted emissions up to 30 MHz while GaN inverters extend to 400 MHz, requiring broadband EMC design strategies. Data derived from patent and literature analysis via PatSnap Eureka. CONDUCTED EMISSION FREQUENCY RANGE SiC MOSFET 150 kHz → 30 MHz GaN HEMT 150 kHz → 400 MHz (13× wider) 150 kHz 30 MHz 400 MHz Source: Graz University of Technology (2022) · PatSnap Eureka analysis · 2014–2025
50+
Patent & literature sources analyzed (2014–2025)
400 MHz
GaN conducted emission upper limit requiring broadband modeling
97.3%
GaN T-type inverter efficiency at 160 kHz (University of Nottingham)
2.5×
Heat sink volume reduction with GaN vs. Si at equivalent power
Noise Source Characteristics

How SiC and GaN Generate Conducted Emissions Differently

Both technologies are wide-bandgap switches, but their switching frequency ranges, voltage classes, and emission spectra place them in fundamentally different EMC design regimes — with implications for every layer of the design stack.

SiC MOSFET · 600 V – 10 kV

Emissions in the 150 kHz–30 MHz Band

SiC MOSFETs switch at 10–100 kHz in high-power inverter applications, with dv/dt rates of 5–50 V/ns. As modeled by the University of Electronic Science and Technology of China (2020), fast switching transients and switching ringing generate high-frequency EMI that can significantly reduce motor drive reliability. The interaction between device parasitics and motor cable impedance is identified as a primary EMI amplification mechanism. DM EMI prediction requires frequency-domain modeling of noise source and propagation path impedances, as formalized by the University of Chinese Academy of Sciences (2017). Learn more about patent landscape analysis for power electronics on the PatSnap platform.

Primary standard: CISPR 11 / CISPR 25
GaN HEMT · Below 650 V

Emissions Extending to 400 MHz and Beyond

GaN HEMTs operate at switching frequencies from several hundred kHz to multiple MHz, producing conducted emissions that extend well into the 30–300 MHz range and beyond — challenging the upper limits of conducted emission standards and impinging on radiated emission territory. Graz University of Technology (2022) demonstrates that GaN systems require an EMC modeling environment covering 150 kHz to 400 MHz, far exceeding what is needed for Si or SiC systems. GaN's superior electron mobility and bandgap enable MHz-range operation, but this comes at the direct cost of broadband conducted and radiated EMI challenges. Explore PatSnap's advanced materials intelligence for semiconductor research.

Dual EMI source: switching + gate-driver CMOS logic
Common-Mode vs. Differential-Mode

SiC CM Noise Amplified by High-Voltage Stray Capacitance

In SiC three-phase inverters, CM noise depends critically on stray capacitances between switching nodes and grounded heat sinks. Virginia Tech (2020) demonstrates that for 10-kV SiC devices, the high switching speed combined with the high voltage rating causes significant EMI and high electric fields, requiring a purpose-designed package architecture. For GaN inverters, National Technical University of Ukraine (2020) shows inrush current at high frequencies causing EMI deviations not predicted by simplified models, highlighting device-level parasitics in CM and DM noise generation in GaN half-bridge circuits. IEC standards govern both modes globally.

SiC: heat-sink capacitance dominant at high voltage
GaN-Specific EMI Source

Gate-Driver CMOS Logic: A Secondary Noise Source Absent in SiC

Kobe University (2022) identifies two primary noise sources in GaN half-bridge power modules: the periodic switching operation of GaN transistors and the logic operation of CMOS gate-driver circuits. This dual-source characteristic is specific to GaN systems and distinguishes their EMI profile from SiC systems, requiring additional high-frequency suppression at the gate-driver supply. EM noise from GaN modules was analyzed up to 6 GHz in that study — a measurement bandwidth that has no precedent in SiC EMC characterization. PatSnap solutions also cover semiconductor packaging innovation.

Analysis bandwidth: up to 6 GHz (Kobe University, 2022)
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Quantitative Comparison

SiC vs. GaN: Key EMC Design Parameters Visualised

Data drawn from peer-reviewed literature and patent filings analyzed via PatSnap Eureka (2014–2025). All values are sourced directly from the cited works.

Switching Frequency Range by Technology

SiC operates at 10–100 kHz in high-power applications; GaN reaches into the MHz range, driving broadband EMC requirements.

SiC MOSFET
GaN HEMT
Switching Frequency Range: SiC MOSFET 10–100 kHz, GaN HEMT 100 kHz to several MHz, GaN T-type at 160 kHz achieves 97.3% efficiency Horizontal range bars comparing typical switching frequency ranges for SiC and GaN inverter topologies, showing GaN's significantly higher operating frequencies that drive broadband EMC design requirements. Source: PatSnap Eureka literature analysis 2014–2025. 10 kHz 100 kHz 1 MHz 10 MHz SiC 10–100 kHz GaN 100 kHz → several MHz 160 kHz 97.3% eff. Source: University of Nottingham (2015), GRIET (2020) · PatSnap Eureka

Parasitic Inductance Management Level

SiC targets busbar/module-level stray inductance; GaN demands sub-nanohenry PCB-level optimization — a fundamentally different design abstraction.

SiC Busbar / Module
GaN PCB Trace / Layout
Parasitic Inductance Design Level: SiC targets busbar/module level (nH range), GaN requires PCB trace optimization (sub-nH, picohenry level) Process-style diagram showing that SiC EMC design addresses stray inductance at the busbar and module packaging level, while GaN demands sub-nanohenry PCB layout optimization where even picohenry-level loop inductances produce voltage overshoot. Source: Xi'an Jiaotong University (2019), Université de Lille (2021) via PatSnap Eureka. SiC Design Hierarchy Stacked Busbar (nH) Power Module Package Gate Drive Resistor Tool: ANSYS Q3D GaN Design Hierarchy PCB Trace (sub-nH, pH) 4-Layer PCB Cell Design Lateral vs. Vertical Layout Tool: ADS S-parameters / FEA Source: Xi'an Jiaotong Univ. (2019), Université de Lille (2021), Oak Ridge National Lab (2018) · PatSnap Eureka

EMI Filter Frequency Coverage Requirement

SiC filters address a well-defined spectral region; GaN filters must cover a far wider range with well-characterized high-frequency parasitic behavior in components.

EMI Filter Frequency Coverage: SiC up to 30 MHz with LCL filters, GaN up to 400 MHz requiring wideband component characterization and full sine-wave output filters Bar chart comparing the EMI filter frequency coverage requirements for SiC and GaN inverter topologies. SiC requires coverage to 30 MHz while GaN demands coverage to 400 MHz — a 13x wider spectrum requiring fundamentally different filter component selection. Source: National Taipei University of Technology (2018), ETH Zurich (2021), Graz University of Technology (2022) via PatSnap Eureka. 400 MHz 300 MHz 200 MHz 100 MHz 30 MHz 30 MHz SiC LCL Filter 400 MHz GaN Wideband + Sine Filter 13× wider range Source: Graz Univ. of Technology (2022), ETH Zurich (2021), National Taipei Univ. of Technology (2018) · PatSnap Eureka

Gate-Drive EMC Optimization Strategies

Gate resistance in SiC creates a direct efficiency–EMI trade-off. Gaussian waveform shaping and multi-objective optimization frameworks resolve the conflict.

SiC Gate Resistance EMI-Efficiency Trade-off: Lower Rg increases switching speed and reduces losses but amplifies conducted EMI; Higher Rg reduces EMI at cost of efficiency. Solutions: Multi-objective optimization (Univ. Cagliari 2020) and Gaussian waveform shaping (Beihang Univ. 2019, 2022) Process diagram illustrating the contradictory effect of SiC MOSFET gate resistance on efficiency and conducted EMI, and the two primary resolution strategies identified in patent literature: multi-objective optimization frameworks and intelligent Gaussian-function-based active gate drive. Source: University of Cagliari (2020), Beihang University (2019, 2022) via PatSnap Eureka. Gate Resistance SiC MOSFET (Rg) Lower Rg ↑ Speed, ↓ Losses ↑ Conducted EMI Higher Rg ↓ EMI ↓ Efficiency Resolution Strategies Multi-Objective Optimization Univ. of Cagliari (2020) Gaussian Waveform Shaping Beihang University (2019, 2022) Source: Univ. of Cagliari (2020), Beihang Univ. (2019, 2022) · PatSnap Eureka

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Head-to-Head Analysis

SiC vs. GaN Conducted EMI Design: Direct Comparison

A dimension-by-dimension comparison across noise spectrum, parasitic management, filter architecture, and application context — drawn directly from 50+ patent and literature sources.

Design Dimension SiC MOSFET GaN HEMT
Switching Frequency 10–100 kHz (high-power inverter)Lower 100 kHz – several MHzHigher
Conducted EMI Band 150 kHz – 30 MHzNarrower 150 kHz – 400 MHz+Broader
dv/dt Rate 5–50 V/ns; high absolute voltage (600 V–10 kV) Sub-ns switching; lower absolute voltage (<650 V)
Parasitic Inductance Focus Busbar & module-level (nH range); ANSYS Q3D optimizationModule PCB trace level (sub-nH, pH); 4-layer PCB, ADS S-paramsPCB
CM Noise Driver Stray capacitance between switching node and heat-sink ground Device-level parasitics; inrush current at high frequency
Gate-Drive EMC Lever Gate resistance trade-off; Gaussian waveform shaping; multi-objective optimizationPrimary Gate-driver CMOS logic is secondary EMI source; HF supply suppression neededSecondary
Output Filter Type LCL filter with custom amorphous-core inductor; winding capacitance management Wideband DM/CM filter; full sine-wave output filter for motor insulation protection
Modeling Bandwidth Routinely to tens of MHz; frequency-domain noise-path modeling Up to 400 MHz (Graz, 2022); up to 6 GHz for gate-driver noise (Kobe, 2022)
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Spread-spectrum modulation data Novel passive suppression circuits IIT Madras inductor-diode patent + 40 more sources
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Innovation Landscape

Who Is Advancing WBG Inverter EMC Design?

Academic research institutions dominate the literature on modeling and fundamental EMC mechanisms. ETH Zurich's Power Electronic Systems Laboratory contributes system-level EMI filter design for GaN motor drives, while Graz University of Technology appears multiple times for broadband EMC modeling extending to 400 MHz. Université Grenoble Alpes contributes across SiC module design, GaN PCB modeling, and multi-cell converter EMC. Beihang University leads in active gate-drive EMI suppression for SiC, with multiple studies on Gaussian-function-based control published in 2019 and 2022.

National laboratories and industrial R&D focus on packaging and system integration. Oak Ridge National Laboratory's 2018 contribution on low-inductance GaN PCB switching cell design is a benchmark for GaN PCB-level EMC design. Virginia Tech addresses 10-kV SiC module packaging for EMI reduction. STMicroelectronics presents electromagnetic simulation flows for SiC MOSFET PCB and filter design targeting EV applications. Explore how power electronics companies use PatSnap for R&D intelligence.

Patent-active assignees include DANA TM4 INC. (inverter housing chamber EMI separation for automotive), Indian Institute of Technology Madras (inductor-diode circuit for WBG DC-DC converters), and ABB Oy Drives (industrial-scale EMC component modeling for AC motor drives using SiC). The dataset reveals an evolution from passive filter-centric EMC design to integrated, simulation-driven approaches combining package-level parasitic optimization, active gate control, and topology selection. Developers can also access PatSnap's open API to integrate patent data directly into R&D workflows.

ETH Zurich
System-level GaN EMI filter design; 2L/3L topology comparison with Si, SiC, GaN
Oak Ridge
Benchmark GaN PCB switching cell; 650 V 3L-ANPC topology, FEA-extracted inductance
Virginia Tech
10-kV SiC MOSFET module package design for reduced CM noise and partial discharge
Beihang Univ.
Gaussian-function active gate drive; open-loop/closed-loop EMI suppression for SiC
Graz Univ.
Broadband GaN EMC simulation to 400 MHz; universally valid simulation environment
IIT Madras
2025 patent: inductor-diode circuit mitigating both CM and DM conducted EMI for WBG
Map the Full Innovator Landscape
Suppression Strategies

EMI Suppression Techniques: What the Patent Literature Reveals

From passive filter design to active gate control and novel circuit topologies — the 2014–2025 dataset shows a clear shift toward integrated, simulation-driven EMC design for both SiC and GaN.

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Spread-Spectrum Modulation (SSM) for Peak Emission Reduction

Politecnico di Torino (2021) shows that SSM reduces peak conducted emission amplitudes in SiC buck converters to achieve EMC standards compliance — but the redistributed noise spectrum may degrade power-line communication channel capacity. A direct trade-off between EMC compliance and PLC system performance that engineers must account for in grid-connected SiC applications.

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GaN PCB Isolation Traces: Compact Filter Co-Location

A 2025 patent from Shenzhen Maidirei Technology introduces a grounded isolation trace on the PCB between the GaN switch and the EMI filter to shield interference while maintaining compactness. The design uses X2 capacitors and common-mode inductors at the input — a practical PCB-level approach to GaN EMI filter integration without sacrificing board area.

Gaussian Active Gate Drive: Unified WBG EMI Suppression

Beihang University (2022) demonstrates that Gaussian-function-based active gate drive can reduce EMI in both SiC and GaN wide-bandgap devices, with parameter tuning governing the EMI–switching-loss trade-off. The earlier 2019 study shows an intelligent open-loop/closed-loop gate control method using a convolution of trapezoidal and Gaussian reference signals can simultaneously reduce voltage and current transition-induced EMI in SiC converters.

🛡️

IIT Madras Inductor-Diode Circuit: Cross-Technology CM/DM Mitigation

A 2025 patent from Indian Institute of Technology Madras directly addresses WBG devices including SiC MOSFETs with a novel passive circuit for mitigating both common-mode and differential-mode conducted EMI — applicable across both SiC and GaN topologies. This represents the emerging class of technology-agnostic WBG EMC solutions that transcend the SiC/GaN design boundary.

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LCL winding capacitance analysis Sine-wave filter sizing for GaN + 40 sources
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Summary

Key Takeaways for Power Electronics EMC Engineers

Seven design principles distilled from 50+ patent and literature sources on SiC and GaN conducted emissions — each traceable to a specific peer-reviewed study or patent filing.

  • SiC inverters produce conducted EMI predominantly in the 150 kHz–30 MHz band, driven by switching frequencies of 10–100 kHz and dv/dt transients of 5–50 V/ns. DM EMI prediction requires frequency-domain noise-path modeling (University of Chinese Academy of Sciences, 2017).
  • GaN inverters extend conducted emissions up to 400 MHz and beyond, requiring broadband simulation environments that far exceed conventional standards coverage (Graz University of Technology, 2022). EM noise from GaN modules has been characterized up to 6 GHz (Kobe University, 2022).
  • Parasitic inductance management differs by abstraction level: SiC targets busbar and module-level stray inductance (Xi'an Jiaotong University, 2019), while GaN demands sub-nanohenry PCB layout optimization where even the choice between single-sided and double-sided PCB layouts measurably changes EMI (Université de Lille, 2021).
  • Gate-drive optimization is a primary EMC lever for SiC: Gate resistance directly trades off efficiency against conducted EMI. Multi-objective optimization frameworks (University of Cagliari, 2020) or Gaussian waveform shaping (Beihang University, 2019, 2022) are required to balance competing objectives.
  • GaN's gate-driver CMOS logic circuits are a secondary EMI source not present in SiC systems (Kobe University, 2022), requiring additional high-frequency suppression at the gate-driver supply — a unique GaN design burden.
  • SiC motor drives require LCL or specialized output filters with custom amorphous-core inductor winding design (National Taipei University of Technology, 2018), while GaN motor drives may additionally require full sine-wave output filters to protect motor insulation at high frequency (ETH Zurich, 2021).
  • Novel cross-technology passive and active suppression circuits are emerging: The IIT Madras inductor-diode circuit (2025) mitigates both CM and DM conducted EMI for WBG converters, while the Shenzhen Maidirei GaN charging circuit patent (2025) introduces grounded PCB isolation traces for compact EMI filter co-location.
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References

  1. Differential Mode Conducted EMI Prediction in Three Phase SiC Inverters — University of Chinese Academy of Sciences, 2017
  2. Modeling and Experimental Investigation of Electromagnetic Interference (EMI) for SiC-Based Motor Drive — University of Electronic Science and Technology of China, 2020
  3. 10-kV SiC MOSFET Power Module With Reduced Common-Mode Noise and Electric Field — Virginia Tech, 2020
  4. Low Stray Inductance Busbar Design and Optimization for SiC-Based Three-Level Device — Xi'an Jiaotong University, 2019
  5. Design of an Integrated Power Module for Silicon Carbide MOSFET with Self-Compensation of the Magnetic Field — Université Grenoble Alpes, 2022
  6. Multi-Objective Optimization of the Gate Driver Parameters in a SiC-Based DC-DC Converter for Electric Vehicles — University of Cagliari, 2020
  7. Shaping SiC MOSFET Voltage and Current Transitions by Intelligent Control for Reduced EMI Generation — Beihang University, 2019
  8. LCL Filter Design with EMI Noise Consideration for Grid-Connected Inverter — National Taipei University of Technology, 2018
  9. Broadband Modeling and Simulation Strategy for Conducted Emissions of Power Electronic Systems Up to 400 MHz — Graz University of Technology, 2022
  10. Parasitic Loop Inductances Reduction in the PCB Layout in GaN-Based Power Converters Using S-Parameters and EM Simulations — Université de Lille, 2021
  11. Design of Low-Inductance Switching Power Cell for GaN HEMT Based Inverter — Oak Ridge National Laboratory, 2018
  12. Analysis of Electromagnetic Noise From Switching Power Modules Using Wide Band Gap Semiconductors — Kobe University, 2022
  13. Wideband Modeling of DC-DC Buck Converter with GaN Transistors — Université Grenoble Alpes, 2021
  14. Input/Output EMI Filter Design for Three-Phase Ultra-High Speed Motor Drive GaN Inverter Stage — ETH Zurich, 2021
  15. The Effect of EMI Generated from Spread-Spectrum-Modulated SiC-Based Buck Converter on the G3-PLC Channel — Politecnico di Torino, 2021
  16. Different Parameter Values of Gaussian Function Analysis on EMI Reduction and Switching Loss in Active Gate Drive of SiC MOSFET — Beihang University, 2022
  17. Single-Phase T-Type Inverter Performance Benchmark Using Si IGBTs, SiC MOSFETs and GaN HEMTs — University of Nottingham, 2015
  18. Optimized Design of 1 MHz Intermediate Bus Converter Using GaN HEMT for Aerospace Applications — Universidad Técnica Federico Santa María, 2021
  19. Advances in Modeling and Suppression Methods of EMI in Power Electronic Converters of Third-Generation Semiconductor Devices — Novosibirsk State Technical University, 2023
  20. Mitigation of Conducted EMI of DC-DC Converter with an Inductor-Diode Based Circuit — IIT Madras, 2025 (Patent)
  21. A GaN Charging Circuit that Resolves EMI Conduction — Shenzhen Maidirei Technology, 2025 (Patent)
  22. International Electrotechnical Commission (IEC) — CISPR 11 and CISPR 25 conducted emission standards
  23. ETH Zurich Power Electronic Systems Laboratory — WBG inverter EMI filter research
  24. Oak Ridge National Laboratory — GaN PCB switching cell design for low-inductance power electronics

All data and statistics on this page are sourced from the references above and from PatSnap's proprietary innovation intelligence platform. Patent and literature analysis covers 2014–2025 across 120+ countries.

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