SiC Wafer Manufacturing 2026 — PatSnap Eureka
Silicon Carbide Wafer Manufacturing: The 2026 Innovation Landscape
SiC wafer manufacturing has become one of the semiconductor industry's most strategically critical technology fields, driven by electric vehicle powertrains, 5G infrastructure, and renewable energy inverters. This landscape examines 30 patent records spanning 2022–2024 across US, CN, JP, and KR jurisdictions.
The Full SiC Value Chain: From Boule to Epitaxy-Ready Substrate
Silicon carbide wafer manufacturing encompasses the full value chain from raw crystal growth through to epitaxy-ready substrate delivery. According to PatSnap's IP analytics platform, the core technology field divides into four interlinked stages: (1) single crystal boule growth, predominantly using physical vapor transport (PVT); (2) wafer slicing and wafering, using wire saws or, increasingly, laser-based methods; (3) surface preparation, including multi-step grinding, lapping, and chemical mechanical polishing (CMP); and (4) epitaxial layer deposition via chemical vapor deposition (CVD) to produce device-ready epi-wafers.
Across the 30 retrieved results, PVT-based crystal growth remains the dominant substrate formation method, while laser slicing is appearing as a disruptive alternative to wire saw cutting with significant material efficiency advantages. Epitaxial quality — particularly defect reduction in basal plane dislocations (BPD), micropipes, stacking faults, and threading dislocations — is a pervasive innovation focus.
The transition from 150mm (6-inch) to 200mm (8-inch) wafer diameter is a defining challenge appearing in at least 5 patents in this dataset, reflecting the industry's drive toward cost reduction through larger substrates. Key technical mechanisms cited include: optimized PVT thermal field design, laser-induced stress crack propagation for kerf-free wafer separation, novel CMP slurry formulations achieving sub-angstrom surface roughness, CVD parameter control for low-dislocation epitaxial layers, and post-growth annealing for stacking fault healing.
The World Intellectual Property Organization (WIPO) tracks SiC as one of the fastest-growing semiconductor patent categories globally, consistent with the 2023 filing volume seen in this dataset.
Innovation Activity Across Technology Clusters and Jurisdictions
Derived from 30 retrieved patent records spanning 2022–2024 from US, CN, JP, and KR jurisdictions. All values reflect the retrieved dataset only.
SiC Patent Records by Technology Cluster
PVT crystal growth and CVD epitaxy dominate the 30-record dataset, with laser slicing and CMP surface engineering as active secondary clusters.
SiC Patent Records by Jurisdiction
The US leads with 14 records, followed by China with 10, reflecting the competitive race between Western incumbents and Chinese domestic developers.
Four Innovation Clusters Defining SiC Wafer Manufacturing
The 30 retrieved patent records organise into four interlinked technology clusters, each representing a distinct stage in the SiC manufacturing value chain.
Physical Vapor Transport (PVT) and 200mm Scale-Up
PVT remains the dominant commercial method for SiC boule growth. Innovation focuses on crucible design, thermal gradient engineering, seed crystal preparation, and atmosphere control to suppress micropipe formation, threading dislocations, and stacking faults. Scaling PVT to 200mm diameter is the most active frontier, with patents from materials science leaders including Wolfspeed, Shandong Tianyue Advanced Technology, Sumitomo Electric, and SICC Co., Ltd. addressing thermal field optimization and defect density management at large diameter.
200mm boule growth · micropipe reduction · thermal gradient controlLaser-Based Slicing: Disrupting Wire Saw with Kerf-Free Separation
Laser slicing is appearing as a disruptive alternative to wire saw cutting with significant material efficiency advantages. Wolfspeed's laser-assisted layer separation uses stress crack propagation to produce thin wafers with minimal material waste. Disco Corporation contributes both a method and apparatus for laser-induced internal stress separation, enabling high-throughput thin wafer production with reduced subsurface crystal damage. Wire saw methods continue to evolve, with Shin-Etsu Chemical addressing warp and total thickness variation (TTV) control through optimized wire tension and slurry parameters.
Laser slicing · kerf-free separation · subsurface damage reduction · TTV controlCMP and Annealing: Achieving Sub-Angstrom Epi-Ready Surfaces
Surface preparation is a critical enabler for epitaxial quality. SKC Co., Ltd. describes a CMP process achieving sub-angstrom surface roughness using a novel slurry composition and pad conditioning method. SK Siltron CSS addresses multi-step grinding and CMP for power device-grade surface finish. Coherent Corp. (formerly II-VI) introduces a substrate annealing method that reduces stacking fault density by more than 50% compared to unannealed substrates through a specific temperature-time profile in a controlled atmosphere. Samsung Electro-Mechanics addresses hydrogen etching for surface preparation prior to epitaxial deposition.
Sub-angstrom CMP · >50% stacking fault reduction · hydrogen etchingCVD Epitaxy: Thick Layers, Low BPD, and Application-Specific Doping
Chemical vapor deposition (CVD) epitaxial growth on SiC substrates is the final step before device fabrication. ROHM Co., Ltd. targets reduced dislocation density and uniform thickness across the wafer surface. Sanan Integrated Circuit addresses stacking fault and basal plane dislocation reduction through optimized CVD precursor flow ratios and temperature profiles. Notably, ROHM also describes thick SiC epitaxial layers greater than 100 micrometers with uniform doping, enabling devices with breakdown voltages greater than 10 kV for grid-scale power conversion and industrial motor drives. Infineon Technologies focuses on nitrogen doping control for EV inverter MOSFET threshold voltage optimization.
CVD epitaxy · >100µm thick layers · >10kV breakdown · BPD reductionKey Patent Assignees in SiC Wafer Manufacturing
The competitive landscape spans Western incumbents and Chinese domestic developers, with active filing programmes across all four technology clusters.
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From Foundational Engineering to Frontier Signals: 2022–2024
The dataset spans late 2022 to mid-2024, with the heaviest cluster of filings in 2023, indicating an actively accelerating field rather than a mature, stable one.
Late 2022 — Foundational Substrate Engineering
The earliest filings in this dataset, from Semiconductor Components Industries, LLC, address wafer structural engineering — trench formation and through-hole architectures in SiC substrates — suggesting mid-stage innovation in substrate geometry customization for improved device performance.
2023 — Volume and Diversity Peak (~20 of 30 Records)
The majority of retrieved records were published in 2023. Key themes include 6-inch and 8-inch crystal growth scaling (Wolfspeed, Tankeblue, Shandong Tianyue), laser slicing systems (Disco Corporation), surface CMP advances (SKC Co., Ltd., SK Siltron CSS), and application-specific substrate optimization for EVs and 5G RF.
Where SiC Wafer Innovation Is Being Deployed
Application-specific substrate optimization is a recurring theme across the dataset, with patents explicitly targeting EV powertrains, 5G RF, high-voltage grid systems, and aerospace.
EV Inverters and On-Board Chargers
Multiple patents explicitly target EV applications. BYD Semiconductor describes a SiC MOSFET fabricated on a 150mm (6-inch) SiC epitaxial wafer for on-board charger and main drive inverter applications. Infineon Technologies AG focuses on SiC power MOSFETs with reduced basal plane dislocation density to improve device reliability in EV inverter environments. According to the International Energy Agency (IEA), the EV market's growth is a primary driver of SiC demand globally, consistent with the volume of EV-targeted filings in this dataset.
150mm SiC MOSFET · BPD reduction · EV inverter reliabilityGaN-on-SiC RF Power Amplifiers for 5G Base Stations
Wolfspeed describes a SiC epitaxial wafer optimized for use as a substrate in GaN-on-SiC RF power amplifier devices for 5G base station applications. The SiC substrate provides high thermal conductivity for heat dissipation from GaN power devices, with optimized surface preparation to reduce GaN nucleation defects. Coherent Corp. (formerly II-VI) also targets semi-insulating SiC substrates for GaN-on-SiC RF applications in defense and 5G communications through controlled resistivity PVT growth and post-growth annealing.
GaN-on-SiC · thermal management · nucleation defect reduction · 5G RFGrid-Scale Conversion and Industrial Motor Drives (>10 kV)
ROHM Co., Ltd. describes a thick SiC epitaxial layer grown on a SiC substrate achieving thickness greater than 100 micrometers with uniform doping and low defect density, enabling fabrication of devices with breakdown voltages greater than 10 kV. Target applications include grid-scale power conversion and industrial motor drives. CRRC Zhuzhou Institute also addresses SiC wafer fabrication optimized for photovoltaic inverter and energy storage applications. The US Department of Energy has identified wide bandgap semiconductors including SiC as critical for grid modernization.
>100µm epi layer · >10kV breakdown · grid-scale power conversionRadiation-Hard Substrates for Aerospace and Defense
Coherent Corp. describes a silicon carbide substrate adapted for aerospace and defense high-power and high-frequency applications. The substrate uses improved PVT growth techniques combined with post-growth processing to achieve ultra-low defect density and controlled electrical properties. The substrate is also designed for radiation-hard device applications, highlighting SiC's suitability for harsh-environment electronics. STMicroelectronics addresses SiC Schottky diodes on substrates with micropipe density below 0.1 cm⁻² for high-temperature operation capability. For further context on advanced materials in high-reliability applications, PatSnap tracks innovation across sectors.
Ultra-low defect PVT · radiation-hard · <0.1 cm⁻² micropipe densityThe SiC Wafer Manufacturing Value Chain
Four interlinked stages from raw crystal growth to epitaxy-ready substrate delivery, each with active patent innovation clusters identified in this dataset.
SiC Wafer Manufacturing: Stage-by-Stage Innovation Map
Each stage corresponds to a patent cluster identified across the 30 retrieved records, with innovation intensity peaking in crystal growth and epitaxial CVD.
Silicon Carbide Wafer Manufacturing — key questions answered
Physical vapor transport (PVT) remains the dominant commercial method for SiC boule growth. Innovation in this cluster focuses on crucible design, thermal gradient engineering, seed crystal preparation, and atmosphere control to suppress micropipe formation, threading dislocations, and stacking faults.
The transition from 150mm (6-inch) to 200mm (8-inch) wafer diameter is a defining challenge appearing in at least 5 patents in this dataset, reflecting the industry's drive toward cost reduction through larger substrates. Challenges include thermal gradient control, defect density management at large diameter, and wafer bow control.
Epitaxial quality — particularly defect reduction in basal plane dislocations (BPD), micropipes, stacking faults, and threading dislocations — is a pervasive innovation focus across the retrieved patent dataset.
Laser slicing is appearing as a disruptive alternative to wire saw cutting with significant material efficiency advantages. Laser-based methods use focused beams to create a modified layer inside the SiC crystal, enabling separation with reduced kerf loss and subsurface damage compared to conventional wire saw slicing.
SiC wafer manufacturing has emerged as one of the most strategically critical technology fields in the semiconductor industry, driven by surging demand from electric vehicle powertrains, 5G infrastructure, renewable energy inverters, and high-voltage industrial systems.
The concentration of 2023–2024 filings reflects a competitive race between Western incumbents (Wolfspeed, Coherent Corp., Infineon, ROHM, STMicroelectronics) and Chinese domestic developers (Sanan Integrated Circuit, BYD Semiconductor, Tianjin Zhonghuan Semiconductor, Tankeblue Semiconductor, Shandong Tianyue).
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References
- Wolfspeed, Inc. — Method for Manufacturing a Silicon Carbide Wafer and a Silicon Carbide Semiconductor Device (US20230295843A1, 2023)
- Wolfspeed, Inc. — Method for Manufacturing a Silicon Carbide Substrate via Laser-Assisted Layer Separation (US20240093407A1, 2024)
- Wolfspeed, Inc. — Process for Growing Large-Diameter SiC Single Crystals with Reduced Threading Dislocations (US20230070833A1, 2023)
- ROHM Co., Ltd. — Silicon Carbide Epitaxial Wafer and Method for Manufacturing the Same (US20240145244A1, 2024)
- ROHM Co., Ltd. — Thick Epitaxial Silicon Carbide Layer for High-Voltage Power Device Applications (US20240170540A1, 2024)
- Disco Corporation — Laser-Based SiC Substrate Slicing with Reduced Subsurface Damage (US20230279577A1, 2023)
- Disco Corporation — Apparatus for SiC Crystal Layer Separation Using Laser-Induced Internal Stress (JP2024022503A, 2024)
- Coherent Corp. (II-VI) — Silicon Carbide Substrate Annealing Method for Reducing Stacking Faults by >50% (US20240096624A1, 2024)
- Coherent Corp. (II-VI) — Silicon Carbide Substrate for High Power, High Frequency Applications (US20230215936A1, 2023)
- Infineon Technologies AG — Silicon Carbide Power MOSFET on SiC Epitaxial Wafer for EV Inverter Applications (US20230207578A1, 2023)
- BYD Semiconductor Co., Ltd. — Silicon Carbide MOSFET Device Fabricated on 150mm SiC Epitaxial Wafer (CN115440806A, 2023)
- Shandong Tianyue Advanced Technology Co., Ltd. — 8-Inch SiC Crystal Growth Method Using Improved Physical Vapor Transport (CN117210925A, 2023)
- Tianjin Zhonghuan Semiconductor Co., Ltd. — 8-inch Silicon Carbide Wafer and Manufacturing Method for Next Generation Power Devices (CN117410172A, 2023)
- Tankeblue Semiconductor Co., Ltd. — Method for Reducing Micropipe Defects in 6-Inch SiC Single Crystal Growth (CN116356408A, 2023)
- SKC Co., Ltd. — Chemical Mechanical Planarization Process for Ultra-Smooth SiC Wafer Surface (KR20230158632A, 2023)
- SK Siltron CSS — Manufacturing Method of Silicon Carbide Substrate Using Grinding and CMP Process (KR20230066831A, 2023)
- Sumitomo Electric Industries, Ltd. — Silicon Carbide Single Crystal Growth Apparatus and Method (JP2023121756A, 2023)
- STMicroelectronics S.r.l. — Silicon Carbide Schottky Diode on High-Quality SiC Substrate (US20240038901A1, 2024)
- Wolfspeed, Inc. — SiC Epitaxial Wafer for 5G RF Power Amplifier Applications (US20230387229A1, 2023)
- World Intellectual Property Organization (WIPO) — Global Patent Activity in Wide Bandgap Semiconductors
- International Energy Agency (IEA) — Electric Vehicle Outlook and Wide Bandgap Semiconductor Demand
- US Department of Energy — Wide Bandgap Semiconductors for Grid Modernization
All data and statistics on this page are sourced from the references above and from PatSnap's proprietary innovation intelligence platform. This landscape is derived from a limited set of patent and literature records retrieved across targeted searches and represents a snapshot of innovation signals within this dataset only. It should not be interpreted as a comprehensive view of the full industry.
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