SiGe Source-Drain Stressors & Hole Mobility — PatSnap Eureka
SiGe Source-Drain Stressors & Hole Mobility in p-Type Nanosheet FETs
Selective epitaxial growth of silicon-germanium into recessed source/drain cavities introduces compressive strain that modifies the valence band structure of p-type channels, boosting hole mobility by up to 100% and drive current in advanced nanosheet gate-all-around architectures.
How Compressive Strain from SiGe Stressors Enhances Hole Mobility
The foundational mechanism of SiGe-induced hole mobility improvement rests on lattice mismatch. Silicon germanium has an intrinsically larger lattice parameter than silicon. When a SiGe layer is grown pseudomorphically within silicon source/drain recesses, it is constrained to match the silicon lattice, placing it under biaxial compression. This constraint is relieved by transferring a uniaxial compressive stress longitudinally into the p-channel between the source and drain.
As established in IBM's foundational patent family (2012), the SiGe layer—kept below its critical thickness to prevent relaxation—matches the underlying Si lattice network and creates a compressive stress component directed into the pFET channel. This mechanism has been replicated across US, WO, EP, JP, and CN jurisdictions by IBM, and is now the industry-standard approach to p-type channel strain engineering. The IEEE has published extensive literature on the band structure physics underlying this enhancement.
The physical consequence of compressive strain is a modification of the silicon valence band structure. Compressive uniaxial strain lifts the degeneracy of the heavy-hole and light-hole bands, reduces inter-band scattering, and lowers the hole effective mass in the transport direction. MIT (2009) reported hole velocity enhancements on the order of 30% from scaled strained-Si₀.₄₅Ge₀.₅₅ channel p-MOSFETs compared to Si control devices. Ballistic velocity simulations further suggested that adding ⟨110⟩ uniaxial compressive strain to Si₀.₄₅Ge₀.₅₅ could produce even more substantial velocity improvements relative to relaxed Si.
Reliability improvements accompany these performance gains. IIT Bombay (2011) demonstrated that a 30-nm thick biaxially strained SiGe (20% Ge) channel on Si shows a ~40% reduction in negative-bias temperature instability, gate leakage, and flicker noise—attributable to a 4% increase in the hole-oxide barrier height in SiGe relative to Si. This dual advantage of performance and reliability makes SiGe stressors particularly attractive for logic p-type devices. For broader context on transistor reliability standards, NIST maintains semiconductor metrology guidelines relevant to strained-Si qualification.
Ge Concentration, Recess Geometry & Epitaxial Process Control
The magnitude of compressive stress is tunable through two independent process variables: germanium mole fraction in the SiGe alloy and the geometry of the source/drain recess itself.
Higher Ge Content = Greater Compressive Stress
As explicitly stated in IBM's WO 2005 patent family, compressive stress in the pFET channel can be adjusted by tuning the Ge concentration in the SiGe layer, since the lattice constant of SiGe is a function of composition. Higher Ge fractions produce larger lattice mismatch and thus greater compressive stress, but risk exceeding the critical thickness for pseudomorphic growth—beyond which misfit dislocations relax the strain and degrade performance.
Yonsei University (2021) found that as Ge concentration increases, high-density defects are generated, which limits applicability—particularly for gate-all-around FETs where epitaxial layer thickness is constrained. The Chinese Academy of Sciences (2017) demonstrated selective Si₁₋ₓGeₓ growth with 0.35 ≤ x ≤ 0.40 and boron doping of 1–3 × 10²⁰ cm⁻³ integrated with high-k and metal gate stacks at the 22 nm node.
~40% Ge: practical upper limit for scaled NSFETsDeeper, Wider Recesses Maximize SiGe Volume & Drive Current
National Cheng Kung University (2017) showed that SiGe growth rate increases with decreased recess width at a fixed depth, and that deeper recesses with a larger depth-to-width ratio promote SiGe {001} facet growth. Higher saturation drain current and lower resistance were achieved by increasing SiGe volume through wider recess width, deeper recess depth, and higher SiGe step height.
This work establishes that process engineers can use recess geometry—not just Ge content—as an independent tuning parameter for drive current optimization. The sigma-shaped S/D recess, studied by Yonsei University, is one geometry specifically evaluated for on-current boosting in logic p-type MOSFETs. PatSnap's materials science tools can map the full recess geometry patent landscape.
Wider + deeper recess = higher saturation drain currentDelta-Layer & In-Situ Boron Doping for Combined Strain + Conductivity
GlobalFoundries' SG 2015 patent introduces delta-layer doping schemes within embedded stressor elements to optimize both strain delivery and electrical performance of the S/D regions simultaneously. KTH Royal Institute of Technology (2020) demonstrated selective epitaxial growth of in-situ doped SiGe on bulk Ge for p+/n junction formation, extending the technique to Ge substrates.
IBM's Ultra-Thin SOI CMOS patents (US, active, 2011) show that eSiGe extensions simultaneously enhance hole mobility while raised S/D structures reduce overall contact resistance, demonstrating that stressor integration and resistance reduction are not competing objectives but can be co-optimized in a single process module.
Boron doping: 1–3 × 10²⁰ cm⁻³ (CAS, 2017)Staying Below Critical Thickness Prevents Strain Relaxation
The SiGe layer must be kept below its critical thickness to prevent relaxation. Above this threshold, misfit dislocations nucleate and propagate, partially or fully relaxing the compressive strain and negating the hole mobility benefit. This constraint becomes increasingly challenging in nanosheet architectures where the available S/D volume is geometrically limited by inner spacer dimensions and nanosheet pitch.
IBM's strained dislocation-free channel patents (US, 2009; EP, 2014) address this by engineering the epitaxial growth conditions and recess profiles to maintain pseudomorphic SiGe layers below the critical thickness across the entire S/D volume, even in aggressively scaled geometries. PatSnap Analytics can map the full dislocation-free channel patent landscape.
Pseudomorphic growth = no misfit dislocationsPatent Filing Trends & Technology Evolution
Over 50 patents and publications spanning 2005–2025 trace SiGe stressor innovation from planar bulk MOSFETs through FinFETs to nanosheet gate-all-around architectures.
Patent Filing Activity by Assignee
IBM leads with 15+ filings across 7 jurisdictions, spanning 2005–2025. Applied Materials and GlobalFoundries are emerging contributors in the nanosheet era.
Technology Evolution: Planar → FinFET → Nanosheet
A clear trend in the data shows evolution from embedded eSiGe in planar bulk MOSFETs (2005–2012) through SOI/FinFET (2012–2018) to nanosheet/GAA-specific strain engineering (2020–2025).
Ge Concentration vs. Stress & Defect Risk
Increasing Ge mole fraction raises compressive stress but generates high-density defects above ~40%, limiting applicability in scaled nanosheet FETs (Yonsei University, 2021).
Hole Mobility Improvement Breakdown
IIT Bombay (2011) demonstrated that a 30-nm biaxially strained SiGe (20% Ge) channel delivers 40% mobility gain vs Si, scaling to 100% in a Si-cap/SiGe stack configuration.
Unique Challenges in Stacked Nanosheet Gate-All-Around Devices
The transition from planar MOSFETs and FinFETs to stacked nanosheet architectures introduces complications for SiGe S/D stressor effectiveness that are unique to multi-channel GAA devices.
Grain Boundary Formation in Multi-Tier Epitaxy
In NSFETs, S/D epitaxy must grow simultaneously from the ends of multiple stacked nanosheet channel layers separated by inner spacers. Because growth initiates independently at each channel level, distinct SiGe crystal grains form at each nanosheet tier and may not merge seamlessly, producing grain boundaries within the S/D epitaxy volume. POSTECH (2022) used fully-calibrated TCAD to show that grain boundaries fully relax channel stresses, splitting the S/D epi into a lower tensile-stress zone and an upper compressive-stress zone.
Doping Profile Perturbation from Tensile Stress Zones
Because tensile stress increases boron diffusivity, the grain boundary in the S/D epi also perturbs doping profiles. The resulting DC performance degradation varies depending on the grain boundary position and inclined angle. POSTECH (2022) found that p-type NSFETs are more severely affected than n-type counterparts by grain boundary-induced stress relaxation. This finding underscores that grain boundary control is a critical yield and performance challenge unique to the nanosheet architecture, with no direct analog in planar or FinFET generations.
Key Patent Assignees & Academic Contributors
The dataset spans more than 50 filings across IBM, Applied Materials, GlobalFoundries, and leading academic institutions from MIT to POSTECH.
| Organisation | Type | Key Contribution | Jurisdictions / Year | Focus Area |
|---|---|---|---|---|
| IBM | Industry | Core eSiGe stressor concept; stressed nanosheet channels; dislocation-free channels; nanowire stressors | US, WO, EP, CN, JP, DE, SG · 2005–2025 | Full stack — planar through GAA |
| Applied Materials | Industry | Contact resistance reduction; strain elements in metallic S/D architecture | US pending 2022; WO 2025 | Nanosheet/GAA contact & strain |
| GlobalFoundries | Industry | Delta monolayer dopants epitaxy for embedded S/D silicide | SG 2015 | Delta-layer doping in stressors |
| MIT | Academic | Hole velocity enhancement ~30% in strained-Si₀.₄₅Ge₀.₅₅ p-MOSFETs; ballistic velocity simulations | Publication, 2009 | Short-channel hole transport physics |
| POSTECH | Academic | TCAD analysis of grain boundary effects in sub-3nm NSFET S/D epi; stress relaxation and doping perturbation | Publication, 2022 | Nanosheet grain boundary simulation |
| IIT Bombay | Academic | 40% mobility gain and 100% in Si-cap/SiGe stack; ~40% NBTI, leakage & noise reduction; 4% barrier height increase | Publication, 2011 | Reliability + performance co-optimization |
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Key Takeaways: SiGe Stressors in p-Type Nanosheet FETs
Seven evidence-based conclusions drawn from 50+ patents and publications, spanning IBM, Applied Materials, and leading academic institutions.
Compressive Strain Directly Enhances Hole Mobility via Valence Band Modification
Compressive strain from SiGe S/D stressors modifies the valence band structure of the p-channel by lifting heavy-hole/light-hole band degeneracy and reducing inter-band scattering. This mechanism was foundationally established by IBM (2012) and has been replicated across multiple jurisdictions and technology nodes. The PatSnap Analytics platform can map every citation of this foundational patent family.
Established: IBM, 2005–201230% Velocity Enhancement; 40–100% Mobility Gains Experimentally Confirmed
MIT (2009) reported ~30% hole velocity enhancement in strained-Si₀.₄₅Ge₀.₅₅ p-MOSFETs. IIT Bombay (2011) demonstrated 40% hole mobility enhancement vs Si and 100% in a Si-cap/SiGe stack, alongside a ~40% reduction in NBTI, gate leakage, and flicker noise. These are the quantitative benchmarks against which all subsequent SiGe stressor work is measured. The SIA tracks industry-wide adoption of these strain techniques.
MIT 2009 · IIT Bombay 2011Ge Mole Fraction and Recess Geometry Are Independent Tuning Parameters
Higher Ge fractions produce greater compressive stress but risk defect generation above ~40% Ge (Yonsei University, 2021). Independently, wider and deeper S/D recesses increase SiGe volume and drive current without changing Ge content (National Cheng Kung University, 2017). Process engineers have two orthogonal handles for optimization. PatSnap's chemistry intelligence tools support epitaxial process optimization research.
Yonsei 2021 · NCKU 2017Grain Boundaries in Multi-Channel NSFETs Fully Relax Channel Stress
POSTECH (2022) showed via TCAD that grain boundaries in NSFET S/D epi fully relax channel stresses, creating tensile/compressive stress zones that perturb doping profiles and degrade DC performance. p-Type NSFETs are more severely affected than n-type. This is a critical yield challenge unique to the nanosheet architecture with no direct planar or FinFET analog. Explore the PatSnap customer case studies for semiconductor R&D applications.
POSTECH 2022 — sub-3nm NSFETsSiGe Source-Drain Stressors & Hole Mobility — key questions answered
Silicon germanium has an intrinsically larger lattice parameter than silicon. When a SiGe layer is grown pseudomorphically within silicon source/drain recesses, it is constrained to match the silicon lattice, placing it under biaxial compression. This constraint is relieved by transferring a uniaxial compressive stress longitudinally into the p-channel between the source and drain. The SiGe layer, kept below its critical thickness to prevent relaxation, matches the underlying Si lattice network and thereby creates a compressive stress component directed into the pFET channel.
MIT (2009) extracted hole velocity enhancements on the order of 30% compared to Si control devices from scaled strained-Si₀.₄₅Ge₀.₅₅ channel p-MOSFETs. IIT Bombay (2011) demonstrated a 40% hole mobility enhancement compared to Si (and 100% in a Si-cap/SiGe stack) from a 30-nm thick biaxially strained SiGe (20% Ge) channel on Si, along with a ~40% reduction in negative-bias temperature instability, gate leakage, and flicker noise.
Higher Ge fractions produce larger lattice mismatch and thus greater compressive stress, but this comes with the risk of exceeding the critical thickness for pseudomorphic growth, beyond which misfit dislocations relax the strain and degrade performance. Yonsei University (2021) found that as Ge concentration increases, high-density defects are generated, which limits applicability—particularly for gate-all-around FETs where epitaxial layer thickness is constrained.
National Cheng Kung University (2017) showed that SiGe growth rate increases with decreased recess width at a fixed depth, and that deeper recesses with a larger depth-to-width ratio promote SiGe {001} facet growth. Higher saturation drain current and lower resistance were achieved by increasing SiGe volume through wider recess width, deeper recess depth, and higher SiGe step height. Process engineers can use recess geometry—not just Ge content—as a tuning parameter for drive current optimization.
In NSFETs, the source/drain epitaxy must grow simultaneously from the ends of multiple stacked nanosheet channel layers separated by inner spacers. Because epitaxial growth initiates independently at each channel level, distinct SiGe crystal grains can form at each nanosheet tier and may not merge seamlessly, producing grain boundaries within the S/D epitaxy volume. POSTECH (2022) found that grain boundaries within the S/D epi fully relax channel stresses. For p-type NSFETs, the grain boundary splits the S/D epi into two zones: the lower region exhibits tensile stress and the upper region exhibits compressive stress. Since tensile stress increases boron diffusivity, the grain boundary also perturbs doping profiles.
IBM's Stressed Nanosheet Channels patent (US, pending, 2025) proposes a semiconductor structure in which a crystalline S/D region transfers longitudinal stress to two or more nanosheet channel layers. Applied Materials' Strain Elements in Metallic Source-Drain Architecture (WO, 2025) takes a complementary approach by intentionally stopping epitaxial growth before crystal structures from adjacent channel tiers merge, and then depositing a compressive stress material to fill the S/D cavity. This strategy preserves the individual epitaxial growth layers and uses the stress material itself as the primary strain source, effectively decoupling epitaxy quality from stress delivery.
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References
- High Performance Stress-Enhanced MOSFETs Using Si:C and SiGe Epitaxial Source/Drain and Method of Manufacture — International Business Machines Corporation, US 2012
- High Performance Stress-Enhanced MOSFETs Using Si:C and SiGe Epitaxial Source/Drain and Method of Manufacture — International Business Machines Corporation, WO 2005
- High Performance Stress-Enhanced MOSFETs Using Si:C and SiGe Epitaxial Source/Drain and Method of Manufacture — International Business Machines Corporation, US 2007 (active)
- Enhanced Hole Transport in Short-Channel Strained-SiGe p-MOSFETs — Massachusetts Institute of Technology, 2009
- Intrinsic Reliability Improvement in Biaxially Strained SiGe p-MOSFETs — Indian Institute of Technology Bombay, 2011
- DC Performance Variations by Grain Boundary in Source/Drain Epitaxy of Sub-3-nm Nanosheet Field-Effect Transistors — POSTECH, 2022
- Effect of Ge Concentration on the On-Current Boosting of Logic P-Type MOSFET with Sigma-Shaped Source/Drain — Yonsei University, 2021
- Effects on Selective Epitaxial Growth of Strained-SiGe p-MOSFETs on Various (001) Si Recess Structures — National Cheng Kung University, 2017
- Integration of Highly Strained SiGe in Source and Drain with HK and MG for 22 nm Bulk PMOS Transistors — Chinese Academy of Sciences, 2017
- Stressed Nanosheet Channels — International Business Machines Corporation, US pending 2025
- Strain Elements in Metallic Source-Drain Architecture — Applied Materials, Inc., WO 2025
- p-FET with a Strained Nanowire Channel and Embedded SiGe Source and Drain Stressors and Methods — International Business Machines Corporation, DE 2012
- Ultra-Thin SOI CMOS with Raised Epitaxial Source and Drain and Embedded SiGe PFET Extension — International Business Machines Corporation, US 2011 (active)
- Delta Monolayer Dopants Epitaxy for Embedded Source/Drain Silicide — GlobalFoundries Inc., SG 2015
- Strained Dislocation-Free Channels for CMOS and Method of Manufacture — International Business Machines Corporation, US 2009
- CMOS Structure with Strained, Dislocation-Free Channels and a Method of Manufacturing the Same — International Business Machines Corporation, EP 2014
- Selective Epitaxial Growth of In Situ Doped SiGe on Bulk Ge for p+/n Junction Formation — KTH Royal Institute of Technology, 2020
- Process Integration to Reduce Contact Resistance in Semiconductor Device — Applied Materials, Inc., US pending 2022
- Four-Period Vertically Stacked SiGe/Si Channel FinFET Fabrication and Its Electrical Characteristics — Chinese Academy of Sciences, 2021
- IEEE — Electron Devices Society (strain engineering publications)
- NIST — Semiconductor Metrology Guidelines
- SIA — Semiconductor Industry Association
All data and statistics on this page are sourced from the references above and from PatSnap's proprietary innovation intelligence platform. Patent analysis performed via PatSnap Eureka.
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