This dataset identifies 27 patent families published between 2015 and mid-2026 that combine SiC MOSFET terminology with architecture-specific claim language such as trench design, planar structures, superjunction geometry and double-trench layouts, filtered against core semiconductor device IPC classes. That is a narrow, claim-language-defined figure, not a count of every SiC MOSFET patent in existence; broader searches on process, packaging or circuit-level claims would return a larger and different set. Filing peaked in 2022 at 8 families and has not been matched since in the data available so far.

The corpus shows a long tail rather than one dominant assignee: the most-cited individual record, US11152503B1 on wave-shaped channel regions, draws noticeably more citations than any other family, but no organisation in the recent-momentum data shows filings in the latest year. Chinese entities account for the majority of receiving-office filings, with China taking 14 of 27 against 8 for the United States, so Chinese research institutes and specialist SiC firms are worth tracking alongside the more visible US filer. Treat any single-company narrative with caution given the small base size.

China, by a clear margin at the receiving-office level: 14 of the 27 families in this dataset were filed through CNIPA compared with 8 through the USPTO, with Europe, South Korea and the PCT route accounting for the remainder. A freedom-to-operate review limited to US filings would miss more than half of the documented architecture claims. This does not necessarily mean Chinese entities hold the most commercially valuable claims, only that they filed the most in this jurisdiction and claim-language window.

In this corpus, planar SiC MOSFET claims typically focus on channel orientation relative to the crystal plane and on reducing channel resistance without extra ion-implanted protection layers, as in the representative EP4492473A1 filing. Trench and double-trench claims more often centre on channel geometry itself, such as the wave-shaped channel regions in the top-cited US filing. Both approaches are actively represented in the highest-cited records, so neither can be read as clearly obsolete or clearly dominant from citation volume alone.

The IPC data shows the corpus is almost entirely concentrated in core H01L semiconductor device structure classes, with only partial overlap into H10D and a single record in H10P, meaning most filings sit squarely on device architecture rather than adjacent process or packaging angles. Sub-areas such as self-aligned planar process integration, crystal-plane-selective channel routing and specific double-trench superjunction combinations appear less densely claimed than the core trench and planar geometry claims. A first filing in these adjacent branches would sit outside the densest citation cluster rather than directly on top of it.