The assignee ranking spans established power-semiconductor manufacturers, Chinese research institutes and universities, and smaller fabless entrants, with 427 families distributed across the field rather than concentrated in a single hand. Some of the most cited foundational filings, such as US20040119076A1 and US5726463A, predate the current wave of Chinese institutional filing and remain reference points for gate structure and JFET-limited designs. Because collaboration is rare in this dataset (only ten co-assignee pairs), most families are held by a single entity, so checking the assignee table directly is more informative than assuming a duopoly.

Filings rose steadily from 19 in 2017 to a peak of 70 in 2023, but the immediately preceding year, 2022, was already at 67, showing that growth had slowed before the peak rather than after it. Part of the apparent drop in 2024-2026 is a publication-lag artefact: patent applications typically publish around 18 months after filing, so the most recent years in any count are always undercounted. A genuine slowdown cannot be confirmed until the later years finish publishing, but the flattening trend through 2022-2023 is real and predates the lag effect.

US10475896B2, assigned to Zhuzhou CRRC Times Electric Co., Ltd. and published in 2019, claims a gate oxide layer built from two sections of different thickness, forming a staircase profile that reduces electric field strength without affecting threshold voltage or gate control, combined with a widened JFET region to cut on-resistance. It does not block gate oxide designs generally; it blocks the specific combination of a stepped multi-thickness gate oxide plus JFET-region widening used to achieve that dual effect. Designs using a uniform-thickness gate oxide, or a different mechanism for field reduction such as shielding structures, sit outside this specific claim combination, though a full clearance opinion should compare claim language directly.

Relative to the dense core of gate oxide and trench-structure claims, this corpus shows comparatively thin coverage in areas like trench sidewall channel mobility enhancement, JFET region width optimisation as a standalone claim element, and avalanche capability under repetitive stress conditions. Power-conversion circuit integration (H02M) is also thin, with only 11 of 427 records touching that subclass, suggesting device-level claims dominate over system-level integration claims. These are not guaranteed clear paths, but they are areas where the claim density in this specific dataset is measurably lower than in the gate oxide and trench core.

China's receiving office leads with 184 filings in this corpus, ahead of the United States at 140, followed by Europe (EPO, 36), the PCT route (28), Japan (16) and South Korea (7). This shifts the practical filing and freedom-to-operate calculus: a review limited to US and European offices would miss the largest single jurisdiction by volume. The PCT figure of 28 also indicates a meaningful share of applicants are still pursuing multi-jurisdiction protection rather than filing nationally from the outset.