Silicon Carbide Trench MOSFET Technology Landscape 2026
Silicon Carbide Trench MOSFET Technology Landscape 2026
SiC trench MOSFETs eliminate the planar JFET resistance bottleneck and achieve lower specific on-resistance, driving EV, renewable energy, and industrial power conversion innovation. This report maps 80+ patent and literature records spanning 1993–2026.
Why SiC Trench MOSFETs Are the Dominant Wide-Bandgap Power Device Architecture
SiC trench MOSFETs are vertical power transistors with the gate electrode buried within a trench etched into the SiC epitaxial stack, enabling channel formation along the trench sidewall. This architecture increases cell density per unit area relative to planar structures and eliminates the JFET resistance component inherent in planar designs. The 4H-SiC polytype dominates retrieved literature due to its isotropic high-field properties and established thermal oxidation pathway for SiO₂ gate dielectrics.
The central engineering problem is the concentration of electric field at the trench bottom corner during off-state blocking, which stresses the gate oxide and limits device voltage ratings and long-term reliability. Solutions span four principal mechanisms: p-type shielding regions beneath the trench bottom, dual-trench architectures that separate gate and shielding functions, integrated Schottky or heterojunction diodes at the trench bottom, and advanced fabrication processes including self-aligned implants and step-etched gate oxide formation.
Among 80+ retrieved records, dominant sub-domains include trench-bottom electric field engineering, integrated freewheeling diode structures, gate charge and Miller capacitance reduction, short-circuit withstand time enhancement, and novel cell topologies such as fin-gate, pi-gate, wave-shaped channel, and grid-pattern source designs. The field has reached commercial maturity for 650 V and 1200 V classes while innovation frontiers push toward 3.3 kV and above.
The geographic landscape shows a clear shift: historically dominated by Japanese companies such as Fuji Electric and US pioneers like Cree/Wolfspeed, the field now features intensive Chinese institutional and startup activity, Taiwanese hardware ODM entry via Hon Hai Precision Industry, and Korean national lab participation from Korea Electrotechnology Research Institute—indicating broad geographic diffusion of SiC trench MOSFET innovation capacity.
Filing Activity, Technology Clusters, and Geographic Shifts in SiC Trench MOSFET Patents
The dataset reveals three distinct periods of SiC trench MOSFET innovation: a foundational period (1993–2006) dominated by Fuji Electric and Cree, a development period (2006–2018) with proliferating assignees, and an acceleration period (2019–2026) characterized by intensive Chinese institutional activity alongside continued Japanese and US innovation.
SiC Trench MOSFET Patent Records by Innovation Period (Dataset, 1993–2026)
The acceleration period (2019–2026) accounts for the largest share of retrieved records, driven by Chinese institutions, Korean national labs, and Taiwanese ODMs entering the field.
↗ Click bars to exploreSiC Trench MOSFET Technology Cluster Distribution (Dataset Records)
Trench-bottom p-shield and electric field mitigation is the dominant cluster, appearing in the majority of retrieved patents, while novel gate topologies and advanced fabrication processes represent the fastest-growing recent clusters.
↗ Click bars to exploreKey Application Areas Driving SiC Trench MOSFET Innovation
SiC trench MOSFETs serve four primary application domains identified in the retrieved dataset, each imposing distinct voltage class, switching frequency, and reliability requirements that shape device architecture choices.
Electric Vehicle Powertrains
SiC trench MOSFETs are enabling devices for main traction inverters in the 650 V–1200 V class, as cited in the 2022 Review of Silicon Carbide Processing for Power MOSFET. Hyundai Motor Company filed US patent 7a010e3e (2014) covering trench SiC MOSFET structures for automotive applications, demonstrating early OEM IP engagement. On-board charger designs also rely on the low switching losses and high thermal conductivity of 4H-SiC trench architectures.
Power ElectronicsRenewable Energy Power Conversion
The 2023 Simulation Study of a 650 V Hybrid-Channel SiC Trench MOSFET explicitly identifies renewable energy applications and data centers as key drivers for 650 V-class devices, noting the need for compact, high-efficiency converter designs. Lower on-resistance and faster switching enabled by trench architecture reduce inverter losses in both solar and wind power systems. Data center UPS systems with server power supplies are also addressed by 650 V class hybrid-channel designs.
Inverter DesignIndustrial and Rail Power Electronics
The 2021 paper on Investigation of 3.3 kV 4H-SiC DC-FSJ MOSFET Structures addresses traction-grade voltage requirements for high-speed rail and industrial motor drive contexts. JSAB Technologies’ pi-type trench gate SiC MOSFET filings (2025–2026) explicitly reference high-speed rail and industrial motor drive use cases. Pushing the trench MOSFET architecture beyond the current 1200 V mainstream toward 3.3 kV represents an active innovation frontier per the dataset’s strategic analysis.
Industrial PowerAerospace and Extreme Environments
NASA SiC device research cited in the dataset includes DC modeling of 4H-SiC nJFET at 500°C, reflecting demand for SiC devices in extreme-temperature environments. The 2021 paper “The Road to a Robust and Affordable SiC Power MOSFET Technology” discusses radiation resistance and high-temperature operation as differentiating SiC advantages over silicon alternatives. These properties position SiC trench MOSFETs for aerospace power management and satellite applications where thermal and radiation environments are severe.
AerospaceLeading Assignees Shaping SiC Trench MOSFET IP Landscape
The dataset shows Fuji Electric as the most prolific single assignee with 10+ filings spanning nearly three decades, while JSAB Technologies represents the fastest-growing new entrant with three US filings in 2025–2026 alone, signaling aggressive Chinese fabless IP buildup.
Top SiC Trench MOSFET Assignees by Filing Count (PatSnap Eureka Dataset)
↗ Click bars to exploreFuji Electric Co., Ltd.
Fuji Electric is the most prolific single assignee in the dataset with at least 10 distinct patent records spanning 1997–2024, filed across US and JP jurisdictions. Key technology areas include the foundational dual-trench Schottky integration concept (1997 US patents ca9dc7fc and 45972c4b), trench MOS structure variants (2008 US ea5acebd), p-channel SiC MOSFETs (2010, 2012), and vertical MOSFET trench gate structures (2018–2024). Multiple filings carry active status, establishing broad foundational coverage in SiC trench MOSFET architecture.
JapanJSAB Technologies (Shenzhen) Ltd.
JSAB Technologies holds three US filings from 2025–2026 (patent IDs fc5dcc1a, 0a4745e4, and 947c2f94) focused entirely on pi-type trench gate SiC MOSFET devices and their fabrication methods. The pi-shaped gate geometry modifies the electric field profile within the gate dielectric region to reduce interface-state-driven mobility degradation, positioning the company as a Chinese fabless entrant aggressively building foundational IP in non-rectangular gate topologies. All three filings are recent and reflect rapid IP accumulation in 2025–2026.
China — CNSix Forward-Looking Trends in SiC Trench MOSFET Innovation (2024–2026)
The most recent filings in the dataset (2024–2026) reveal six distinct forward-looking directions, from first-class reliability targets and self-aligned manufacturing to non-conventional gate geometries and multi-auxiliary gate structures for short-circuit performance.
Bipolar Degradation Suppression as a First-Class Design Target
II-VI Delaware’s 2026 US patent (90717676) features a buried p-well along the trench sidewall explicitly designed to prevent bipolar degradation alongside dielectric breakdown. This reflects growing recognition that stacking fault growth from body diode operation is a commercial reliability limiter in deployed SiC trench MOSFET products. The explicit pairing of bipolar degradation prevention with conventional oxide protection signals a maturing understanding of field failure modes.
Self-Aligned Manufacturing for Volume Cost Reduction
Hon Hai Precision Industry filed both a US and EP patent in 2026 (2707e54d and 3d8eb3e3) targeting self-alignment techniques that reduce lithography overlay sensitivity in SiC trench MOSFET manufacturing. Fraunhofer’s 2021 DE patent (5c435d86) demonstrated a lithography-free process using thermally oxidized polysilicon fill as an implantation mask. Together, these filings signal a broader industry movement toward self-aligned fabrication as volumes scale and cost-of-manufacturing barriers become commercially critical.
Conventional Trench MOSFET vs. Split-Gate / Dual-Trench SiC MOSFET: Key Dimensions
Click any row to explore further.
| Dimension | Conventional Single Trench MOSFET | Split-Gate / Dual-Trench MOSFET |
|---|---|---|
| Gate Oxide Stress at Trench Bottom | High — gate oxide directly exposed to concentrated drain-side electric field during off-state blocking | Reduced — lower source-connected shield electrode or deeper Schottky trench screens gate oxide from peak field |
| Miller Capacitance (Cgd) | Higher gate-drain overlap capacitance, increasing switching losses and gate drive requirements | Reduced gate-drain overlap capacitance via split polysilicon gate; Alpha and Omega Semiconductor split-gate patents (2012, 2013 US) specifically target this metric |
| Third-Quadrant / Body Diode Performance | Parasitic bipolar body diode with ~3 V forward drop causes bipolar degradation and high reverse recovery charge | Integrated Schottky or heterojunction diode at second trench suppresses parasitic body diode activation; Fuji Electric 1997 dual-trench concept is foundational |
| Cell Pitch / Process Complexity | Simpler single-trench process; fewer mask steps; established manufacturing baseline | Additional trench etch and fill steps; self-aligned variants (Hon Hai 2026, Fraunhofer 2021) aim to reduce lithography overlay sensitivity |
| Short-Circuit Withstand Time (SCWT) | Limited by gate oxide thermal stress and body diode current crowding; baseline SCWT determined by cell architecture | Laterally widened p-shield region (1200 V literature, 2022) and auxiliary depletion-mode pMOS (2023 literature) achieve up to 1.92× SCWT improvement |
| Voltage Class Demonstrated | Commercially mature at 650 V and 1200 V; research activity extending toward 3.3 kV | Dual-trench and super-junction structures (DC-FSJ, back-side super-junction) specifically targeting 3.3 kV class per 2021–2022 literature records |
| Representative Assignees | Cree/Wolfspeed (2002–2011), Korea Electrotechnology Research Institute (2022, 2025), ZJU-Hangzhou Center (2023) | Fuji Electric (1997–2024), Alpha and Omega Semiconductor (2012–2013), United Silicon Carbide (2016–2017), JSAB Technologies (2025–2026) |
Frequently Asked Questions: SiC Trench MOSFET Technology
During off-state blocking, the electric field concentrates at the trench bottom corner and directly stresses the gate oxide, limiting device voltage ratings and long-term reliability. Because SiC has a critical electric field roughly 10× higher than silicon, the oxide at the trench bottom can be exposed to fields that exceed safe oxide operating limits without deliberate shielding. This is why the majority of retrieved patents—covering p-shield regions, dual-trench architectures, and self-aligned implants—specifically target trench-bottom electric field management.
A p-type shielding region placed beneath or at the corners of the gate trench electrostatically screens the gate oxide from high drain-side fields during blocking. Connectivity schemes vary: Fuji Electric (2008 US patent ea5acebd) couples the bottom layer to the base layer via the trench sidewall end without a dedicated shield electrode; Toyota (2017 US patent bf49f285) confines the p-type layer to the corner of the trench bottom only; Korea Electrotechnology Research Institute (2022 US patent 84aac563) forms a bottom protection well with the source electrode covering the entire epitaxial surface for simplified interconnection.
The parasitic bipolar body diode in SiC trench MOSFETs has approximately a 3 V forward drop and causes bipolar degradation and high reverse recovery charge when operating in inverter bridges. Integrating a low-forward-voltage unipolar diode—either a Schottky or heterojunction diode—directly into the trench suppresses body diode activation. Fuji Electric introduced the dual-trench Schottky concept in 1997; Novus Semiconductors’ 2024 US patents extend this to high-speed flyback diode integration. The dataset’s strategic analysis states that third-quadrant performance is now a mandatory specification, not optional.
In a split-gate trench architecture, the polysilicon gate is divided into an upper gate region and a lower source-connected shield electrode within the same trench. The lower shield electrode directly reduces the gate-drain overlap capacitance by blocking the field coupling between the gate and the drain-side semiconductor. Alpha and Omega Semiconductor’s 2012 and 2013 US patents (543e4217 and 64915b1f) establish this approach for SiC power devices. United Silicon Carbide’s 2016 WO patent (9200d2a7) describes a self-aligned version with further reduced Miller capacitance.
According to the dataset’s geographic analysis, Chinese entities collectively account for a significant fraction of 2023–2026 filings. The most active Chinese organizations include JSAB Technologies (Shenzhen) with three US filings in 2025–2026 on pi-type gate structures, Nanjing Third Generation Semiconductor Technology Innovation Center (2026 EP), Hubei Jiufengshan Laboratory (2024 EP and US), Hefei Anhi Semiconductor (2024–2025 US), ZJU-Hangzhou Global Scientific and Technological Innovation Center (2023 US), Shanghai Xindao Electronic Technology (2025 CN), and China Zhenhua Group Yongguang Electronics (2026 CN).
Three fabrication innovations are prominent in the dataset: Applied Materials’ channeled implantation (2022–2023 US patents 26d00b53 and 9763f49f) creates a highly uniform current spreading layer with concentration profile variation of 5× or less in 4H-SiC; Fraunhofer’s 2021 DE patent (5c435d86) describes a lithography-free self-aligned process using thermally oxidized polysilicon as an implantation mask; and Shanghai Xindao’s 2025 CN patent (54829bd3) introduces stepped epitaxy where a first gate oxide of 200–500 nm is formed before the main epitaxial stack to separately control trench-bottom and sidewall oxide thicknesses.
Data and insights on this page are based on a limited patent and literature dataset and are for reference only. Figures may not represent the complete technology landscape.