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Silicon Wafer Patents: Who Leads, Where Filings Cooled 2026

Silicon Wafer Patents: Who Leads, Where Filings Cooled 2026
https://www.patsnap.com/resources/blog/rd-blog/silicon-wafer-manufacturing-patent-landscape/ · Patsnap · data cut-off 2026-07-31 · downloaded from the live page
Patent Landscape · Semiconductors
Silicon Wafer Manufacturing Patents: Crystal Growth, Slicing and Polishing Claims
  • Filing has cooled, not grown. activity peaked in 2018 at 15 filings and has since drifted down toward single digits, with the most recent full year sitting well below the midpoint.
  • Claims cluster tightly around two IPC classes. H01L (132 records) and C30B (88 records) between them cover most of the corpus, meaning grinding and polishing under B24B (29 records) carries comparatively thin coverage.
  • The most-cited prior art is two decades old. the top-cited record, US6336968B1 on non-oxygen precipitating Czochralski wafers, still sits above every recent filing in citation count — a sign the foundational claims were staked early and rarely re-litigated.
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176
Published Records
56%
Top-5 Share of All Records
-70%
Filing Growth 2021→2024
US
Leading Jurisdiction

Filing growth compares 2021 (10 records) with 2024 (3) — a three-year span. 2024 is the most recent year we treat as complete: publication lags filing by roughly 18 months, so 2025 onwards are still filling in and any growth rate that ends there would understate the field. Top-5 share is the combined record count of the five largest assignees divided by all 176 records in scope (CR5), not by the ranked leaders only.

Published byPatsnap Research··7 min readSourced from Patsnap Eureka
Overview

What this landscape covers

This dataset tracks 176 patent families filed against silicon wafer manufacturing between 2015 and mid-2026, drawn from documents that combine Czochralski crystal growth, wafer slicing and surface-finishing terms with claims touching crystal defect control, oxygen concentration, flatness, edge profile or polishing. The IPC scope spans C30B15 (crystal growth), H01L21 (semiconductor device processing) and B24B37 (grinding and polishing), which is why the composition skews so heavily toward growth and device-processing classes rather than pure mechanical finishing.

Filing counts for the most recent year are necessarily incomplete: publication typically lags the underlying filing by around eighteen months, so 2025 and 2026 will fill in further as records publish. The decline visible from the 2018 peak through the 2022 midpoint is real, but the very last data points should be read as a floor, not a final count.

Filing activity and technology composition, 2017–2026
  1. 1SUMCO CORP33
  2. 2SHIN ETSU HANDOTAI CO LTD25
  3. 3SUNEDISON INC23
  4. 4GLOBALWAFERS JAPAN11
  5. 5SILTRONIC AG6
  6. 6GLOBALWAFERS CO LTD6
  7. 7INTERNATIONAL BUSINESS MACHINE CORPORATION5
  8. 8XIAN ESWIN MATERIAL TECHNOLOGY CO LTD4
  9. 9TEXAS INSTRUMENTS INC4
  10. 10SEMICON COMPONENTS IND LLC3
Source: Patsnap Eureka. Assignee ranking and totals. Derived from a Patsnap search on Silicon Wafer Manufacturing covering 2015–2026, data cut-off 2026-07-31. Counts reflect published records only and shift as new filings publish.Run this in Eureka MCP

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Data

Filing trends and technology composition

Two views of the same 176-family corpus: filings by year, and where those filings sit across the IPC classes that define the search.

A peak already behind the field

Filings rose from 9 in 2017 to a peak of 15 in 2018, then eased back to roughly 4 by the 2022 midpoint and continued lower toward the most recent partial year. That shape reads as a maturing claim space rather than a growing one — the foundational mechanics of crystal growth and wafer finishing were staked out early in the window, and later years show fewer net-new filers rather than a wave of new entrants.

A peak already behind the field048111592017152018201920202021202220232024202512026Most recent year is partial — publication lag means later filings are not yet visible.

Growth and device processing dominate

H01L (132 records) and C30B (88 records) anchor the corpus, consistent with a search built around Czochralski growth and semiconductor device processing. B24B grinding and polishing (29), C23C coating (15) and G01N testing (13) are present but comparatively thin, suggesting the mechanical finishing and inspection steps around the core crystal-growth claims are less densely claimed than the growth step itself.

Growth and device processing dominateH01L · Semiconductor devices13275.0%C30B · Crystal growth8850.0%H10P7341.5%B24B · Grinding & polishing2916.5%C23C · Coating & surface deposition158.5%G01N · Material analysis & testing137.4%B28D · Working stone52.8%H10D · Semiconductor devices (general)52.8%Other116.3%

Shares are the percentage of the 176 records in scope. A patent can carry several IPC classes, so the shares add up to more than 100%.

Source: Patsnap Eureka. Filing trend and technology composition. Derived from a Patsnap search on Silicon Wafer Manufacturing covering 2015–2026, data cut-off 2026-07-31. Counts reflect published records only and shift as new filings publish.

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Key Patents

The prior art still doing the most work

Representative Filing
US20240203745A12024-06-20

Silicon wafer manufacturing method (Shin-Etsu Handotai, 2024)

SHIN-ETSU HANDOTAI CO., LTD.

The method grinds front and back wafer surfaces to a specified arithmetic surface roughness, then applies isotropic whole-surface dry-etching to remove the mechanically damaged layer left by grinding, followed by a bounded double-side polishing step with a defined stock-removal limit per surface.Filed as US20240203745A1 by SHIN-ETSU HANDOTAI CO., LTD., published 2024-06-20.

US20240203745A1 — patent drawing 1
View full record
Most-cited records in the corpus
#Publication no.Patent titleCitations
1US6336968B1Non-oxygen precipitating czochralski silicon wafers76
2US5474020AOxygen precipitation control in czochralski-grown silicon cyrstals69
3JP1998275905ASilicon wafer manufacturing method and silicon wafer56
4US5795381ASIO probe for real-time monitoring and control of oxygen during czochralski growth of single crystal silicon53
5US5744401ASilicon wafer manufacturing method eliminating final mirror-polishing step49
6US6277501B1Silicon epitaxial wafer and method for manufacturing the same46
7US5329733AWafer slicing and grinding machine and a method of slicing and grinding wafers33
8US20170018457A1Semiconductor Device Comprising an Oxygen Diffusion Barrier and Manufacturing Method31
9JP2007208060ASilicon wafer, manufacturing method therefor, and silicon block27
10JP1998144698ASilicon wafer and its manufacture26

Citation counts favour older records simply because they have had longer to accumulate citations inside this corpus — read them as markers of influence on later filings, not as current state of the art.

Each row carries its publication number; clicking a row searches Eureka by that number.

Source: Patsnap Eureka. Citation counts and representative records. Derived from a Patsnap search on Silicon Wafer Manufacturing covering 2015–2026, data cut-off 2026-07-31. Counts reflect published records only and shift as new filings publish.Run this in Eureka MCP
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Insights

What the numbers mean for filing strategy

Four read-outs from the trend, composition and citation data that matter more than the raw counts on their own.

Filing Momentum
15 → ~1
peak year to latest partial year

The wave has passed, publication lag aside

Even allowing for the roughly 18-month gap between filing and publication, the drop from the 2018 peak through the 2022 midpoint to the latest count is too steep to be lag alone. New entrants are filing less often than they were a decade ago.

Filing trend, 2017–2026
Claim Density
132 + 88
H01L and C30B record counts

Growth and device-processing claims dominate

Two IPC classes account for the bulk of the corpus. Anyone filing new crystal-growth or device-processing claims should expect dense prior art; anyone filing on the mechanical finishing side has more room.

IPC composition
Jurisdictional Spread
46 / 31 / 31
US / China / EPO filings

Filing is concentrated across three offices, not one

The United States leads with 46 filings, but China and the EPO each sit close behind at 31. Japan (23) and South Korea (13) round out a genuinely multi-jurisdictional filing pattern rather than a single home market.

Receiving office counts
Foundational Prior Art
76 citations
top-cited record, US6336968B1

The oldest claims still carry the most weight

The most-cited record in the corpus addresses non-oxygen precipitating Czochralski wafers and predates most of the filing window. Oxygen-concentration control remains a reference point that later filings are measured against.

Most-cited records
Eureka AI Agent
Looking for what nobody has claimed yet?

Eureka can read the same corpus for gaps instead of for coverage: under-claimed branches adjacent to silicon wafer manufacturing, with the prior art for and against each one.

Find the white space →
Source: Patsnap Eureka. Co-assignee relationships and derived observations. Derived from a Patsnap search on Silicon Wafer Manufacturing covering 2015–2026, data cut-off 2026-07-31. Counts reflect published records only and shift as new filings publish.Run this in Eureka MCP
Players

Who holds the ground, and who has stopped filing

Recent-year momentum tells a different story from cumulative counts: the assignees most associated with this space show no filings in the latest tracked year, which either reflects publication lag or a genuine pause in new claims.

Momentum Signal
0 in latest year
across every tracked top assignee

No tracked leader shows recent-year activity

SUMCO, SunEdison, Shin-Etsu Handotai, GlobalWafers Japan, Texas Instruments and IBM all show zero filings in the latest tracked year, with GlobalWafers Japan down 100% year-on-year. This is consistent with publication lag but also with a genuinely quieter filing period across the field's established names.

Recent-year momentum by assignee
Collaboration Pattern
4 pairs
co-assignee pairs identified

Co-filing is rare and mostly internal

Only four co-assignee pairs appear in the corpus, the strongest linking IBM's corporate entity to its own French IP department, and two others linking Shin-Etsu Handotai to individual named inventors. This is a field of solo filers more than joint ventures.

Co-assignee pairs
Jurisdictional Reach
6 offices
US, China, EPO, Japan, South Korea, WIPO

Established players file broadly, not just at home

The spread across six receiving offices, with the US, China and the EPO each drawing double-digit filings, indicates the assignees active here treat this as a global claim space rather than a single-market one.

Receiving office counts
🔍
Under-claimed sub-areas worth a first-mover look
These sit inside the searched IPC scope but carry visibly thinner filing density than crystal growth or core device processing.
Dry-etch damage-layer removal post-grindingEdge-profile control on large-diameter wafersIn-line oxygen concentration sensingDouble-side polishing stock-removal limitsCoating-based defect suppression (C23C)
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Recent-year filing momentum by assignee
AssigneeRecent yearYoY
SUMCO Corporation0
SunEdison, Inc.0
Shin-Etsu Handotai Co., Ltd.0
GlobalWafers Japan Co., Ltd.0-100%
Texas Instruments Incorporated0
International Business Machines Corporation (IBM)0
Sumitomo Metal Industries, Ltd.0
Siltronic AG0
Source: Patsnap Eureka. Assignee-level momentum. Derived from a Patsnap search on Silicon Wafer Manufacturing covering 2015–2026, data cut-off 2026-07-31. Counts reflect published records only and shift as new filings publish.Run this in Eureka MCP
What's Next

Where to take this analysis

The trend and composition data point to specific next questions for anyone deciding where to file or where to license.

Test a claim against the dense classes

Before drafting in H01L or C30B, run the proposed claim language against the most-cited prior art in those classes to see how much room actually remains.

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Watch for the lag catching up

The apparent drop-off after 2022 will partially fill in as 2025-2026 filings publish. Re-check assignee momentum in a few months rather than treating the current gap as final.

Track filing trends in Eureka

Look at the under-claimed finishing steps

B24B, C23C and G01N together carry far fewer records than the growth classes, which is where a narrower first-filing claim is more likely to clear prior art.

Run a white space search in Eureka
Source: Patsnap Eureka. Forward-looking reading of the same dataset. Derived from a Patsnap search on Silicon Wafer Manufacturing covering 2015–2026, data cut-off 2026-07-31. Counts reflect published records only and shift as new filings publish.Run this in Eureka MCP
FAQ

Common questions about silicon wafer manufacturing patents

Answers are grounded in the same dataset. Derived from a Patsnap search on Silicon Wafer Manufacturing covering 2015–2026, data cut-off 2026-07-31. Counts reflect published records only and shift as new filings publish.Run this in Eureka MCP

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Disclaimer. This page is generated from Patsnap Eureka data drawn from a limited snapshot of global patent and scientific-literature records, and is provided for general information and reference only.

Patent data carries inherent limitations: recent filings (typically the most recent 18–24 months) are under-counted due to standard publication lag; counts may be reported at either a patent-family or a patent-record basis and are not always directly comparable; classification, applicant-name, and citation data may contain errors, duplicates, or omissions; and the underlying search query defines and constrains the scope shown. As a result, the analysis may be incomplete or inaccurate and may not reflect the full technology landscape.

Nothing on this page constitutes an exhaustive prior-art, novelty, freedom-to-operate, or validity search, nor does it constitute legal, financial, investment, or professional advice, and it should not be relied upon as such. Any patent, commercial, or strategic decision should be verified independently and reviewed with qualified patent, legal, and domain professionals. Patsnap makes no warranties, express or implied, as to the accuracy, completeness, or fitness for any particular purpose of the information presented.

Machine translation. Assignee and organisation names originally recorded in Chinese, Japanese or Korean have been rendered into English by an AI translation step so that the tables stay readable. These renderings are best-effort and may not match a company’s registered English name; the original name is what the underlying patent record carries, and it is what any Eureka query launched from this page uses.

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