Single Photon Avalanche Diode Technology Landscape 2026
Single Photon Avalanche Diode Technology Landscape 2026
SPADs enable detection of individual photons with picosecond-level timing resolution, driving applications from automotive LiDAR to quantum communications. Approximately 60% of active patent filings in this dataset were published after 2019, confirming accelerating commercialization.
SPAD Innovation: From Foundational Physics to Megapixel Arrays
Single Photon Avalanche Diodes are reverse-biased p-n junction photodetectors biased above breakdown voltage, where a single photo-generated carrier triggers a macroscopic, detectable current pulse. Key performance metrics include photon detection efficiency (PDE), dark count rate (DCR), timing jitter (FWHM), afterpulsing probability, and fill factor.
The dataset spans foundational silicon CMOS implementations through advanced III-V compound semiconductor structures and emerging 2D material platforms. Device geometries range from single-pixel discrete detectors to megapixel focal plane arrays. Circuit integration—particularly quenching and reset circuits—is a co-equal design challenge alongside the diode structure itself.
The field divides into three epochs across 80+ retrieved records. The foundational era (pre-2008) established avalanche multiplication principles and early integrated readout architectures. The CMOS integration era (2008–2019) made standard CMOS compatibility the dominant design goal. The optimization and scaling era (2020–present) is defined by pixel pitch reduction and advanced node integration.
Sony Semiconductor Solutions demonstrated a 3.06 μm pixel-pitch SPAD with 57% PDE and deep trench isolation in 2023. STMicroelectronics filed active SPAD patents for 28 nm FD-SOI technology in 2021 and avalanche pixel control circuits in 2024–2025. Adaps Photonics filed multiple US and WO patents for bonded-substrate SPAD arrays between 2021 and 2023.
Technology Cluster Distribution and CMOS Node Progression
Four technology clusters emerge from this dataset: standard CMOS-integrated silicon SPADs, enhanced-architecture NIR SPADs, III-V and heterogeneous material SPADs, and large-format SPAD arrays. Each cluster reflects distinct engineering trade-offs and application targets.
SPAD Technology Cluster Distribution by Retrieved Record Count
Standard CMOS-integrated silicon SPADs form the largest cluster, reflecting the dominant design goal of CMOS process compatibility across the dataset.
↗ Click bars to exploreSPAD Publication Activity by Epoch (Pre-2008, 2008–2019, 2020–2025)
The optimization and scaling era (2020–present) accounts for approximately 60% of active patent filings in this dataset, reflecting accelerating commercialization activity.
↗ Click bars to exploreKey SPAD Application Verticals: LiDAR, Biophotonics, Quantum, and Beyond
SPAD technology serves multiple distinct application domains in this dataset, each demanding specific device parameter trade-offs. The four primary verticals—automotive LiDAR, biophotonics and medical imaging, quantum communications, and high-energy physics—are detailed below with named institutions and measured results.
Automotive LiDAR and 3D Ranging
The most commercially active application domain in this dataset. Hewlett Packard Labs (2019) demonstrated a P+/N-well junction SPAD in 0.18 μm CMOS with breakdown voltage below 10 V, explicitly targeting cost and voltage minimization for LiDAR. Southwest Institute of Technical Physics fabricated 64×64 Si SPAD and InGaAsP/InP SPAD focal plane arrays for driverless vehicle LADAR platforms (2018).
Automotive SensingBiophotonics and Medical Imaging
EPFL AQUA (2019) reviewed SPAD-based endoscopic FLIM, super-resolution microscopy, NIROT, and PET implementations with pixel-level time-stamping. Fondazione Bruno Kessler’s NUV-HD SiPM achieved 63% PDE at 420 nm with 75–100 ps coincidence resolving time for PET scintillator readout. Columbia University (2016) demonstrated a 72×60 angle-sensitive SPAD array for lens-free 3D fluorescence lifetime mapping at micrometer scale.
Medical ImagingQuantum Communications and Photonics
IFN-CNR / Politecnico di Milano (2020) benchmarked SPAD performance against superconducting nanowire single-photon detectors, identifying SPAD advantages in room-temperature operation and scalability. University of Geneva (2007) demonstrated free-running InGaAs/InP SPAD operation with 10% detection efficiency at less than 2 kHz noise for fiber-optic quantum key distribution. National University of Singapore (2013) confirmed radiation tolerance of Si APDs for satellite-based quantum communication at 400 km orbit.
Quantum PhotonicsHigh-Energy Physics and Space Astronomy
University of Geneva (2022) developed a Picosecond Avalanche Detector proof-of-concept in 130 nm SiGe BiCMOS for charged-particle tracking with picosecond timestamps, while University of Barcelona (2010) compared HV 0.35 μm vs. 0.13 μm CMOS for particle collider tracking detectors. University of Hawaii (2022) tested a 1-megapixel HgCdTe linear-mode APD array at 50 K achieving approximately 3 electrons per pixel per kilosecond dark current for exoplanet spectroscopy.
Physics and AstronomyLeading SPAD Patent Assignees in This Dataset
Among active patent filings retrieved, STMicroelectronics and Adaps Photonics show the highest SPAD-specific activity. STMicroelectronics spans device structures to advanced-node quenching circuits, while Adaps Photonics concentrates IP on a specific bonded-substrate 3D integration platform.
Top SPAD Patent Assignees by Retrieved Filing Count
↗ Click bars to exploreSTMicroelectronics R&D Limited
STMicroelectronics is the most prolific commercial SPAD patent assignee in this dataset, with at least 3 active patents spanning 2019–2025 across EP and FR jurisdictions. Key filings include a deep n-well/p-substrate SPAD for CMOS circuits (EP, 2020), a 28 nm FD-SOI active quenching and reset circuit enabling sub-40 ps avalanche detection and 50% afterpulsing reduction (2021), and avalanche pixel control circuit patents filed in 2024–2025 in France. Their IP trajectory covers CMOS node migration from standard process through advanced FD-SOI technology.
Europe — EP / France — FRAdaps Photonics Inc.
Adaps Photonics filed 4 retrieved active patents between 2021 and 2023 across US and WO jurisdictions, all covering bonded logic-sensor substrate SPAD array architectures. This concentrated IP cluster—spanning US (2021, 2022, 2023) and WO (2021) filings—indicates a focused strategy around a specific 3D stacked-die platform that decouples optical optimization of the SPAD from transistor scaling of the readout logic. All 4 retrieved patents carry active legal status.
United States — US / WOFive Forward-Looking SPAD Innovation Directions (2022–2025)
Based on the most recent filings and publications in this dataset, five forward-looking directions are identifiable: sub-4 μm pixel pitch arrays, advanced CMOS node integration, 3D stacked sensor-logic architectures, metasurface and photon-trapping nanostructures, and Sb-based or Ge/GeSn heterogeneous SPADs for SWIR.
Sub-4 μm Pixel Pitch SPAD Arrays Approaching DRAM-Class Scaling
Sony Semiconductor Solutions demonstrated a 3.06 μm SPAD pixel with 57% PDE, 0.4% crosstalk, and 15.8 cps DCR using two-step deep trench isolation and an embedded metal optical shield (2023). This trajectory points toward megapixel SPAD sensors competitive with conventional image sensors for consumer and automotive applications. Pixel pitch is now the primary competitive metric in high-resolution photon counting imaging.
28 nm FD-SOI Integration Enabling Sub-40 ps Avalanche Detection
STMicroelectronics’ 28 nm FD-SOI active quenching and reset circuit (2021) uses body biasing to detect avalanche events in under 40 ps and reduce afterpulsing charge by 50%. Subsequent avalanche pixel control circuit patents filed in 2024–2025 signal that advanced node integration is becoming commercially deployable. This CMOS node migration is identified as the primary competitive battleground for cost-sensitive high-volume markets.
Silicon CMOS SPADs vs. III-V Compound Semiconductor SPADs
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| Dimension | Silicon CMOS SPADs | III-V Compound SPADs |
|---|---|---|
| Wavelength Range | 300–1000 nm (silicon bandgap limited); NIR enhanced variants up to ~1000 nm | 1310/1550 nm telecom (InGaAs/InP, InGaAs/InAlAs); UV (GaN/AlN); SWIR up to 2.5 μm (Sb-based, Ge/GeSn) |
| Peak PDE | 57% at 3.06 μm pixel pitch (Sony, 2023); 63% at 420 nm for NUV-HD SiPM (FBK, 2019); ~20% at 785 nm in 180 nm CMOS | 26% at 1550 nm at 210 K (University of Sheffield, 2016); 38% SPDE at 1310 nm at 125 K (Ge-on-Si, University of Glasgow, 2019) |
| Timing Jitter | 7.8 ps FWHM at 65 nm node (Université de Sherbrooke, 2018); 100 ps CRT for PET readout (FBK) | 70 ps at 1550 nm (InGaAs/InAlAs, University of Sheffield, 2016) |
| Operating Temperature | Room temperature standard; DCR below 10 kHz at 15°C in 180 nm CMOS (ICube/CNRS, 2016) | Typically requires cooling: 210 K for InGaAs/InAlAs (Sheffield, 2016); 125 K for Ge-on-Si (Glasgow, 2019); 50 K for HgCdTe (Hawaii, 2022) |
| CMOS Compatibility | Monolithic integration demonstrated at 65 nm, 130 nm, 180 nm, 350 nm nodes; zero-change 0.18 μm process (HP Labs, 2019) | Not directly CMOS compatible; requires heterogeneous integration or separate fabrication; Ge-on-Si approaches CMOS compatibility |
| Afterpulsing | 0.2% in 180 nm CMOS (ICube/CNRS, 2016); 50% reduction via FD-SOI body biasing in sub-40 ps detection (STMicroelectronics, 2021) | InAlAs avalanche region shows reduced afterpulsing vs. InP; Ge-on-Si achieves significantly reduced afterpulsing vs. InGaAs/InP (Glasgow, 2019) |
| Key Commercial Assignees | STMicroelectronics, Sony Semiconductor Solutions, Adaps Photonics, PixArt Imaging, AMS AG | University of Sheffield, University of Glasgow (research stage); KETEK GmbH (SiPM) |
| Pixel Pitch Scaling | Down to 3.06 μm demonstrated (Sony, 2023); approaching DRAM-class scaling | N/A — pixel pitch scaling not a primary reported metric in retrieved III-V literature |
Frequently Asked Questions: SPAD Technology and Patents
A SPAD is a reverse-biased p-n junction photodetector biased above its breakdown voltage (excess bias). When a single photon is absorbed, the resulting photo-generated carrier triggers a self-perpetuating avalanche of charge carriers, producing a macroscopic, detectable current pulse. Key performance metrics include photon detection efficiency (PDE), dark count rate (DCR), timing jitter (FWHM), afterpulsing probability, and fill factor.
This dataset documents SPAD implementations at 65 nm (Université de Sherbrooke, 7.8 ps FWHM), 130 nm (imec, 13% PDE at 905 nm), 150 nm, 180 nm (ICube/University of Strasbourg, DCR below 10 kHz at 15°C), 350 nm (Vrije Universiteit Brussel CASPAD), and 28 nm FD-SOI (STMicroelectronics, sub-40 ps avalanche detection). Zero-change 0.18 μm CMOS integration was demonstrated by Hewlett Packard Labs in 2019 for LiDAR.
Sony Semiconductor Solutions demonstrated a 3.06 μm pixel-pitch SPAD with 57% photon detection efficiency, 0.4% optical crosstalk, and 15.8 cps dark count rate in 2023, using two-step deep trench isolation and an embedded metal optical shield. This represents the leading performance in silicon SPAD array scaling as evidenced by this dataset.
STMicroelectronics (Research & Development) Limited is identified as the most prolific commercial SPAD patent assignee in this dataset, with at least 3 active patents across EP and FR jurisdictions spanning 2019–2025. Adaps Photonics Inc. has 4 retrieved active patents (2021–2023) all covering bonded logic-sensor substrate SPAD array architectures across US and WO jurisdictions. PixArt Imaging holds 3 active or pending image sensor patents with SPAD-based pixel circuits filed through 2025.
Silicon SPADs are limited by the silicon bandgap to wavelengths roughly below 1000 nm and operate at room temperature, but offer direct CMOS compatibility. III-V SPADs such as InGaAs/InAlAs achieve 26% PDE at 1550 nm (University of Sheffield, 2016) and Ge-on-Si planar SPADs achieve 38% SPDE at 1310 nm (University of Glasgow, 2019), but typically require cooling to 125–210 K and are not directly CMOS compatible. Sb-based and Ge/GeSn materials are emerging for SWIR coverage to 2.5 μm.
Five forward-looking directions are identified in filings and publications from 2022–2025: (1) sub-4 μm pixel pitch arrays approaching DRAM-class scaling; (2) 28 nm FD-SOI integration enabling sub-40 ps avalanche detection; (3) 3D stacked bonded sensor-logic architectures; (4) metasurface and photon-trapping nanostructure PDE enhancement without DCR or jitter degradation; and (5) Sb-based and Ge/GeSn heterogeneous SPADs extending single-photon sensitivity to the 1.5–2.5 μm SWIR band.
Data and insights on this page are based on a limited patent and literature dataset and are for reference only. Figures may not represent the complete technology landscape.