Spin-Orbit Torque MRAM Technology Landscape 2026
Spin-Orbit Torque MRAM Technology Landscape 2026
SOT-MRAM delivers sub-nanosecond write speeds and decoupled read/write paths, positioning it as the leading candidate for next-generation non-volatile cache. This report synthesises approximately 60 patent records and literature sources spanning 2009–2026.
How SOT-MRAM Separates Write and Read Paths
SOT-MRAM replaces the conventional two-terminal STT write path with a three-terminal geometry. An in-plane write current flows through a spin-orbit coupling layer — typically a heavy metal such as Ta, W, or Pt — generating a transverse spin current via the spin Hall effect. This spin current switches the free layer of an MTJ without passing current through the tunnel barrier.
The read path remains through the MTJ pillar, entirely decoupling read and write operations. This eliminates the read-disturb problem endemic to STT-MRAM and enables substantially faster write speeds down to sub-nanosecond timescales, lower write energy, and improved endurance compared to incumbent STT-MRAM designs.
Core technology sub-domains in this dataset include perpendicular magnetic anisotropy SOT devices, SOT–STT hybrid architectures, field-free switching solutions, multi-state and differential cell architectures, SOT channel materials engineering, and two-terminal SOT-MRAM. Each addresses a distinct aspect of commercialisation readiness for cache and embedded memory applications.
The filing timeline spans from foundational STT-MRAM array architecture patents from Qualcomm in 2009 through an identifiable SOT-MRAM emergence phase in 2016–2019 and into a 2022–2026 advanced-integration cluster featuring stacked 3D architectures, bismuth-based SOT channel materials, and advanced peripheral circuit designs from IBM, Samsung, IMEC, UMC, and Stanford University.
SOT-MRAM Patent Activity by Phase and Technology Cluster
The filing timeline identifies four distinct phases: a pre-2015 foundational STT-MRAM substrate, a 2016–2019 SOT-MRAM emergence phase, a 2019–2022 architecture diversification phase, and a 2022–2026 advanced-integration cluster. Technology cluster activity spans perpendicular PMA devices, hybrid SOT–STT architectures, multi-state cells, and channel materials engineering.
SOT-MRAM Patent Records by Technology Cluster
Perpendicular PMA SOT devices and SOT–STT hybrid architectures represent the two most patent-active clusters in this dataset, followed by multi-state/differential cells and channel materials engineering.
↗ Click bars to exploreSOT-MRAM Filing Activity by Innovation Phase (2009–2026)
The 2022–2026 advanced-integration phase represents the highest concentration of new filings in this dataset, driven by IBM, Samsung, UMC, and Stanford University entries.
↗ Click bars to exploreKey SOT-MRAM Application Areas Across Memory Hierarchy and Computing
SOT-MRAM patent activity in this dataset targets five principal application domains: non-volatile cache replacement, embedded non-volatile memory for SoC platforms, storage-class memory, neuromorphic and in-memory computing, and cryogenic computing infrastructure.
Non-Volatile L2/L3 Cache Replacement
Literature demonstrates 400 ps switching in perpendicular SOT-MRAM structures, meeting L2/L3 cache latency requirements. Qualcomm’s SOT-assisted STT-MRAM hybrid (2018–2019, US/WO/EP/IN) and area optimisation literature (2021) explicitly target this workload. IBM’s stacked SOT-MRAM (2025, US) is oriented toward density-constrained embedded cache integration with multiple vertical MRAM cell stacks above a single bottom electrode.
Cache MemoryEmbedded NVM for SoC and MCU
Qualcomm’s filings from 2009 to 2022 across US, CA, EP, IN, and CN jurisdictions reflect sustained investment in integrating MRAM arrays into mobile SoC platforms. TSMC’s boosted-gate-voltage programming patents (2009–2012, US/EP) and UMC’s 4T1M SOT-MRAM circuit (2025, US) address peripheral circuit design for eNVM integration at advanced nodes. UMC’s bottom-pinned SOT-MRAM (2024, US) further targets foundry-compatible process integration.
Embedded MemoryStorage-Class Memory High-Density Arrays
ISSI’s vertical-transistor SOT-MRAM (2023, US) increases bit-cell density by reducing transistor footprint. IBM’s stacked vertical SOT cell (2025, US) explicitly fabricates multiple MRAM cell stacks vertically above a single bottom electrode with a shared low-resistivity inter-stack rail, enabling 3D density scaling. Haikang Group’s multi-MTJ array patents (2020–2021, CN) represent the most concentrated Chinese domestic portfolio targeting this domain.
Storage-Class MemoryNeuromorphic and In-Memory Computing
IBM’s multi-state SOT-MRAM (2022, US/WO) uses two MTJs of differing diameters sharing a common metal rail, enabling multiple resistance states from a single SOT current source for analog weight storage in neuromorphic inference. Qualcomm’s differential SOT cell (2019, US) uses two MTJ storage elements on a common SOT conductive layer with opposing bit lines, improving sense margin for in-memory computing array designs.
Neuromorphic ComputingLeading SOT-MRAM Patent Holders: IBM, Qualcomm, Samsung, and More
IBM leads dedicated SOT-MRAM patenting with at least 9 distinct records spanning 2022–2026, while Qualcomm dominates mobile/SoC MRAM with at least 8 records from 2009–2019. Haikang Group holds the most concentrated Chinese domestic portfolio with at least 6 CN-jurisdiction active patents. The US–China duopoly in SOT-MRAM patent activity reflects global technology competition in advanced memory.
Top SOT-MRAM Assignees by Filing Count (2009–2026)
↗ Click bars to exploreInternational Business Machines Corporation
IBM is the most prolific dedicated SOT-MRAM assignee in this dataset with at least 9 distinct records across US and WO jurisdictions filed from 2022 to 2025. Key patent areas include multi-state SOT-MRAM (2022, US/WO), SOT/STT hybrid stacks (2023, US/WO), low-resistivity SHE write lines (2022/2024, US/WO), stacked 3D SOT-MRAM (2025, US), doubled SOT-metal-layer architecture (2025, US), and perpendicular SOT structures (2025, US). The majority of IBM’s filings are active and concentrated in the US, with WO and CN counterparts for select records.
United StatesQualcomm Incorporated
Qualcomm is the dominant mobile/SoC MRAM applicant in this dataset with at least 8 distinct records spanning 2009 to 2019 across US, WO, EP, IN, and CN jurisdictions. Key filings include foundational STT-MRAM array design patents (2009–2014), the SOT-assisted STT-MRAM hybrid filed simultaneously in WO, US, EP, and IN (2018–2019), and the differential SOT-MRAM cell structure (2019, US active). Qualcomm’s multi-jurisdiction simultaneous filing of the SOT-STT hybrid signals strong commercial intent for SoC embedded memory integration.
United StatesSix Forward-Looking Directions in SOT-MRAM Innovation
Based on filings dated 2023–2026 in this dataset, six forward-looking directions are identifiable, ranging from field-free switching solutions and bismuth-based channel materials to two-terminal cell geometries and advanced peripheral circuit integration.
Field-Free Deterministic Switching via Structural Engineering
The external magnetic field requirement for deterministic PMA switching remains a key commercialisation barrier. Haikang Group (CN pending, 2025) uses local ion implantation into the SOT channel to create a flip-control region. IBM’s perpendicular SOT patent (US pending, 2025) and the CAS Institute field-free array (US active, 2026) use structural designs that break in-plane symmetry through SOT-channel geometry to achieve deterministic switching without an external field.
Thermally Stable Bismuth-Based SOT Channel Materials
IMEC VZW’s bismuth-based SOT layer patents (2023 US, 2023 EP, 2026 US) represent a pivot away from conventional Ta/W/Pt heavy metals toward topological-insulator-class materials offering larger spin Hall angles. The materials must also satisfy thermal budget constraints of BEOL CMOS integration at annealing temperatures above 400°C. The high-melting-point metal co-constituent (melting point ≥1000°C) in IMEC’s formulation addresses this thermal stability requirement.
SOT-MRAM vs. STT-MRAM: Key Dimensions
Click any row to explore further.
| Dimension | SOT-MRAM | STT-MRAM |
|---|---|---|
| Write Path | Separate in-plane write current through SOC layer (three-terminal); no current through tunnel barrier during write | Write current passes through MTJ tunnel barrier (two-terminal); combined read/write path |
| Write Speed | Down to sub-nanosecond (400 ps demonstrated in Ta/FeCoB/MgO/FeCoB MTJ structures, literature 2018) | Slower write speeds; SOT-STT hybrid shows 80% reduction in switching time vs. pure STT |
| Write Energy | Lower write energy; SOT-STT hybrid demonstrates >70% reduction in write energy vs. pure STT-MRAM | Higher write energy; tunnel barrier current increases write energy and wear |
| Read-Disturb | Eliminated — read and write paths are decoupled; read current does not pass through free layer during write | Read-disturb problem present due to combined read/write path through MTJ |
| Cell Terminals | Typically three-terminal (SOT channel + MTJ); two-terminal variants in development (Stanford, 2025 WO) | Two-terminal; more compact baseline cell |
| Field-Free Switching | Requires structural engineering for deterministic PMA switching (active area: CAS 2026, IBM 2025, Haikang 2025) | No external field requirement for in-plane magnetisation variants; PMA STT also field-free |
| Endurance | Improved endurance vs. STT-MRAM due to absence of write current through tunnel barrier | Tunnel barrier degradation limits endurance under repeated write cycling |
| Key Assignees (Dataset) | IBM (9+ records, 2022–2025), Qualcomm (SOT-STT hybrid, 2018–2019), Samsung (2024–2025), IMEC VZW (2020–2026) | Qualcomm (foundational array patents 2009–2014), TSMC (gate-voltage boosting 2009–2012), Avalanche Technology (PMA multilayer 2010–2016) |
Frequently Asked Questions: SOT-MRAM Technology and Patents
SOT-MRAM uses a three-terminal geometry where an in-plane write current flows through a spin-orbit coupling layer — typically a heavy metal such as Ta, W, or Pt — generating a transverse spin current via the spin Hall effect that switches the MTJ free layer without passing current through the tunnel barrier. This separates the read and write paths, eliminating the read-disturb problem endemic to STT-MRAM and enabling write speeds down to sub-nanosecond (400 ps demonstrated in literature).
IBM is the most prolific dedicated SOT-MRAM assignee with at least 9 distinct records across US and WO jurisdictions covering multi-state architectures, SOT/STT hybrid stacks, low-resistivity SHE write lines, perpendicular SOT structures, stacked 3D SOT-MRAM, and doubled SOT-metal architectures — all filed between 2022 and 2025. Qualcomm follows with at least 8 records spanning 2009–2019, and Haikang Group holds the most concentrated Chinese domestic portfolio with at least 6 CN-jurisdiction active patents from 2020–2025.
Perpendicular magnetic anisotropy SOT-MRAM requires an external magnetic field for deterministic switching, which is a key commercialisation barrier. In this dataset, solutions include local ion implantation into the SOT channel to create a flip-control region (Haikang Group, CN pending, 2025), structural SOT-channel geometry designed to break in-plane symmetry (IBM, US pending, 2025), and structural design of the SOT word line and MTJ array (CAS Institute, US active, 2026).
IMEC VZW’s bismuth-based SOT layer patents (2023 US, 2023 EP, 2026 US) represent a pivot from conventional Ta/W/Pt heavy metals toward topological-insulator-class materials that offer larger spin Hall angles. These materials must also satisfy BEOL CMOS integration thermal budgets above 400°C annealing temperatures. IMEC addresses this by combining the bismuth-based compound with a high-melting-point metal (melting point ≥1000°C), delivering both large spin Hall angle and thermal stability.
The most frequently cited target application is non-volatile cache memory (L1/L2/L3 replacement), with 400 ps switching demonstrated sufficient for L2/L3 latency. Other domains include embedded non-volatile memory for SoC and microcontrollers (Qualcomm, TSMC, UMC), storage-class memory and high-density arrays (ISSI, IBM stacked architecture, Haikang Group), neuromorphic and in-memory computing (IBM multi-state cells, Qualcomm differential cell), and cryogenic computing infrastructure (SanDisk Technologies, 2020).
The US is the dominant filing jurisdiction in this dataset, with the majority of records filed by IBM, Qualcomm, Samsung, IMEC, UMC, and others. China represents a significant cluster from Haikang Group (6+ active CN patents, 2020–2025) and the Institute of Microelectronics, Chinese Academy of Sciences (3 US-jurisdiction patents). Limited cross-filing overlap between US-centric and China-centric filers suggests potential market access and licensing complexity as both ecosystems develop in parallel.
Data and insights on this page are based on a limited patent and literature dataset and are for reference only. Figures may not represent the complete technology landscape.