Spin Qubit Silicon Quantum Dot Arrays 2026 — PatSnap Eureka
Spin Qubit Silicon Quantum Dot Arrays 2026
Silicon spin qubits are transitioning from few-qubit demonstrations toward medium-scale processors with 2D connectivity and foundry-scale fabrication. This dataset spans more than 60 patent and literature records from 2005 to 2026.
Silicon Spin Qubits: From Proof-of-Concept to Foundry Scale
Silicon spin qubits confine individual electrons or holes in gate-defined quantum dots fabricated in silicon or silicon-germanium heterostructures, with the spin state encoding a qubit. Three primary substrate platforms appear in this dataset: silicon metal-oxide-semiconductor (SiMOS), strained Si/SiGe heterostructures, and strained Ge/SiGe systems, alongside phosphorus donor-based approaches.
Key physical challenges addressed across retrieved records include valley degeneracy in the silicon conduction band, charge noise from dielectric interfaces, the need for isotopic purification to eliminate nuclear spin bath decoherence, and scalable readout methods not requiring a dedicated charge sensor per qubit. Arrays from double quantum dots up to 3×3 two-dimensional grids are documented.
Publication dates in this dataset span 2005 to 2026, revealing four identifiable phases: a foundational phase establishing long-coherence-time donor qubits; a development phase reaching 99.6% single-qubit fidelity; a scaling phase validating 300 mm wafer fabrication; and a current maturation phase integrating on-chip control electronics and all-optical lithography.
In this dataset, NewSouth Innovations Pty Limited is the most prolific patent assignee with four distinct filings across three jurisdictions, while Intel Corporation and MIT hold one and two filings respectively. The eight patents with explicit jurisdiction data in retrieved records show US and WO filings dominating for spin qubit-specific IP.
Filing Trends and Technology Cluster Distribution
Retrieved records reveal four technology clusters — SiMOS, Si/SiGe, CMOS foundry, and Ge/SiGe hole spin — with filing and publication activity accelerating from 2019 onward as foundry-scale and 2D array demonstrations multiplied.
Patent & Literature Records by Technology Cluster (Dataset Snapshot)
In this dataset, CMOS foundry-compatible arrays and Si/SiGe heterostructure clusters account for the largest share of retrieved records, reflecting the field’s push toward scalable fabrication.
↗ Click bars to exploreRecords by Innovation Phase and Period (Dataset Snapshot)
In this dataset, the maturation and commercial phase (2022–2026) shows the highest concentration of recent filings, with foundry-scale fabrication and charge noise engineering driving new records.
↗ Click bars to exploreWhere Silicon Spin Qubit Arrays Are Being Deployed
Records in this dataset map spin qubit silicon quantum dot technology to four distinct application domains: universal quantum computing, quantum error correction, quantum simulation, and quantum sensing for industrial non-destructive evaluation.
Universal Quantum Computing
The dominant application focus across this dataset is scalable universal quantum computation. The Spiderweb Array (2022) proposes a 2D array with ~12 μm pitch to accommodate on-chip sample-and-hold circuits, reducing off-chip wire count. A 3×3 array design (2021) demonstrates execution of Grover’s algorithm more efficiently than linear array counterparts.
Quantum ComputingQuantum Error Correction
Multiple records address error detection requirements directly. The Silicon Quantum Computing Pty Limited patent (US 2023) frames donor-based singlet-triplet qubits explicitly in terms of fault tolerance, with donor electron spin lifetimes up to 30 s. Pauli spin blockade is identified as a local parity measurement tool for error detection in integrated SiMOS platforms (2018).
Error CorrectionQuantum Simulation
Ge 2×2 arrays and GaAs/AlGaAs 2×2 arrays are motivated in part by Fermi-Hubbard model quantum simulation according to 2018 and 2020 records in this dataset. Valley physics in silicon offers a distinct route, with valley-based qubit encoding proposed for noise-resilient computation in a 2012 record. Controllable inter-dot tunnel couplings in 2D arrays enable Hubbard model parameter tuning.
Quantum SimulationIndustrial Quantum Sensing
Two Chinese patents in this dataset address quantum sensing for industrial non-destructive evaluation. State Grid Anhui Electric Power Research Institute filed a CN patent (2023 pending) for a quantum sensing frontend using solid-state spin probes for magnetic flux leakage detection. Anhui Guosheng Quantum Technology filed a CN patent (2024 pending) for a solid-state spin quantum probe and quantum magnetic flux leakage detector.
Industrial NDT SensingKey Patent Assignees in Spin Qubit Silicon Quantum Dots (Retrieved Records)
In this dataset, NewSouth Innovations Pty Limited holds the largest filing count among named patent assignees with five filings across three jurisdictions (US, WO, AU), representing the UNSW spinout ecosystem’s sustained IP campaign on SiGe alloy valley splitting engineering and advanced processor architecture.
Patent Filings per Assignee — Spin Qubit Silicon Quantum Dots (Dataset Snapshot)
↗ Click bars to exploreNewSouth Innovations Pty Limited
NewSouth Innovations is the most prolific patent assignee in this dataset with five filings spanning 2021–2025 across US, WO, and AU jurisdictions. Its core IP covers silicon-germanium alloy-based quantum dots with increased alloy disorder and enhanced valley splitting (US 2023 active, WO 2023, AU 2023 pending, US 2025 active), plus an advanced quantum processor architecture filing (WO 2021). These patents target the persistent low-valley-splitting problem in Si/SiGe by placing Ge content within the quantum well itself to raise valley splitting and improve device yield.
AustraliaIntel Corporation
Intel Corporation holds one active US patent (2023) in this dataset covering quantum dot-based qubit devices with on-chip microcoil arrangements that provide gradient magnetic fields for EDSR-driven individual qubit addressability in spin qubit arrays. This filing represents Intel’s Tunnel Falls program approach to solving the qubit addressability challenge in dense arrays. The patent is an active US filing as of 2023.
United StatesFive Forward-Looking Technology Directions (2022–2026)
The most recent filings and publications in this dataset (2022–2026) reveal five discernible forward-looking directions: 300 mm all-optical fabrication, charge noise engineering, SiGe alloy valley splitting, coherent spin shuttling, and modular quantum-classical integration.
Foundry-Scale 300 mm All-Optical Fabrication
A 2022 record demonstrated 300 mm all-optical-lithography fabrication at a ²⁸Si/²⁸SiO₂ interface with relaxation times exceeding 1 s and coherence above 3 ms, eliminating electron-beam lithography from qubit production. A 2021 record on uniform spin qubit devices in an all-silicon 300 mm integrated process reported reproducible interdot coupling control in the 2–100 GHz range and valley splitting of approximately 150 μeV. This is identified as a critical enabler for commercial-scale production.
Charge Noise Engineering via Thin Quantum Wells
A 2023 record demonstrated that 5 nm thick ²⁸Si quantum wells in Si/SiGe heterostructures significantly reduce charge noise, with a measured minimum of 0.29 ± 0.02 μeV/Hz½ at 1 Hz. This systematic material-to-device-performance mapping has direct impact on CZ-gate fidelity and represents a newly maturing subfield. With single-qubit fidelities approaching fault-tolerance thresholds, two-qubit gate fidelity limited by charge noise is identified as the dominant remaining performance gap.
SiMOS vs. Si/SiGe Heterostructure Spin Qubit Platforms
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| Dimension | SiMOS (Si/SiO₂) | Si/SiGe Heterostructure |
|---|---|---|
| Confinement interface | Si/SiO₂ — thermal oxide | Strained Si quantum well in SiGe barrier |
| Valley splitting | Large and tunable via electrostatic gate fields | Low and variable; key engineering challenge |
| Best reported single-qubit fidelity | 99.6% (isotopically enriched ²⁸Si, 2014) | N/A (fidelity records not separately cited in this dataset) |
| Array scale demonstrated | 2×2 CMOS array (2020); 3×3 design proposed (2021) | 12-dot linear array (2016); 4-dot quadruple QD (2019) |
| Fabrication compatibility | 300 mm all-optical lithography (2021, 2022) | 300 mm foundry fabrication validated (2020) |
| Charge noise level | Higher interface disorder than Si/SiGe | Minimum 0.29 ± 0.02 μeV/Hz½ at 1 Hz (5 nm well, 2023) |
| Coherence times | T₂* = 120 μs; relaxation >1 s; coherence >3 ms (2022) | Tunnel couplings tunable to 20 GHz (2019) |
| Key IP assignee (this dataset) | NewSouth Innovations / Silicon Quantum Computing | NewSouth Innovations (SiGe alloy valley splitting patents) |
Frequently Asked Questions: Spin Qubit Silicon Quantum Dot Arrays
Three primary substrate platforms appear in this dataset: silicon metal-oxide-semiconductor (SiMOS) confining electrons at the Si/SiO₂ interface, strained Si/SiGe heterostructures using a silicon quantum well in a SiGe barrier, and strained Ge/SiGe systems for hole spin qubits. A fourth sub-domain involves phosphorus donors in silicon where the donor nuclear or electron spin functions as the qubit.
Silicon has conduction band valley degeneracy — the ‘valley problem’ — where multiple low-energy states exist that can hybridize with the spin qubit states and cause decoherence. In SiMOS, valley splitting is large and tunable via electrostatic gate fields. In Si/SiGe heterostructures, valley splitting is low and variable, making it a key materials engineering challenge. The NewSouth Innovations patent family (2023–2025) addresses this by placing Ge content within the quantum well itself to raise valley splitting and improve device yield.
A 2014 record for a SiMOS addressable quantum dot qubit in isotopically enriched ²⁸Si reported 99.6% single-qubit fidelity via randomized benchmarking, with T₂* = 120 μs. A 2022 record for a silicon FinFET hole qubit operating above 4 K reported single-qubit fidelity at the fault-tolerance threshold with Rabi frequencies up to 150 MHz.
Arrays ranging from double quantum dots up to 3×3 two-dimensional grids and linear 12-dot chains are documented in this dataset. Specific examples include a 12-dot linear Si/SiGe array with nine active quantum dots (2016), a 2×2 CMOS nanowire array with integrated charge sensing (2020), a planar Ge 2D array with single-charge occupancy (2021), and a 3×3 array design demonstrating Grover’s algorithm execution (2021).
Spin shuttling moves an electron spin coherently across multiple quantum dots in a linear array, providing long-range qubit connectivity beyond nearest-neighbor exchange coupling. A 2022 record demonstrated a shuttling-based two-qubit logic gate with exchange on/off ratio exceeding 1000 and spin coherence preservation of 99.6% per hop. A 2020 simulation record modeled charge shuttling at approximately 300 m/s. This mechanism is identified as essential for 2D processor scaling.
Among named patent assignees in this dataset, NewSouth Innovations Pty Limited (Australia/UNSW spinout) holds five filings across US, WO, and AU jurisdictions on SiGe valley splitting and processor architecture. Intel Corporation holds one active US patent (2023) on on-chip microcoil arrangements for spin qubit arrays. MIT holds two WO filings (2025, 2026) on modular quantum system-on-chip architectures. Silicon Quantum Computing Pty Limited holds one US patent (2023) on donor-based singlet-triplet qubits.
Data and insights on this page are based on a limited patent and literature dataset and are for reference only. Figures may not represent the complete technology landscape.