It refers to an architecture where the pixel sensor array and the readout or logic circuitry are fabricated on separate dies and joined vertically, typically through hybrid bonding or through-silicon vias, rather than laid out on a single planar chip. Claims in this space usually specify the interconnect pitch, the layer order (pixel chip over logic chip, or the reverse), and sometimes a rerouting layer that reconciles different pitches between the two dies. The representative record in this landscape, US20170309667A1, is a clean example of that last pattern. Reviewing a claim for this feature means checking whether it recites a specific pitch relationship or interconnect structure, since that is usually where infringement turns.

The assignee ranking behind this landscape returns only 8 companies, and it is heavily concentrated: the leading filer holds 43 of the ranked records, compared with 2 at fifth place. That is a steep drop rather than a gradual tail, which means a competitive review should weight the leader’s portfolio far more heavily than the rest of the ranked list. Because the ranking is small, it should not be described as a top-50 or top-100 list — it is the whole set the data returns.

Filing activity peaked at 6 records in 2020, held near that level in 2021, and fell to 0 by 2024 — a -100% swing over that three-year span. However, publication lags filing by roughly 18 months, so 2025 and 2026 figures in any dataset are still incomplete and will revise upward as more records publish. The honest read is that the pace has cooled through the last complete year on record, not that the technology area has ended.