Storage Class Memory Patents: Leaders, Trends & White Space 2026
- Filing has cooled since its 2019 peak. 29 families published that year against a flat-to-declining run through the low single digits by 2022, so the claim space that got staked early is largely settled.
- The docket concentrates almost entirely in one office. 123 of 139 published records are US filings, with China, WIPO, the UK and the EPO together accounting for the rest — this is a US-centred prosecution story.
- G06F carries the whole dataset; G11C is a distant second. Every record touches electric digital data processing (G06F), while dedicated memory-device IPC codes like G11C and H10B show up in a minority of filings, pointing to a system- and controller-level focus over device physics.
What this patent set actually covers
Storage class memory sits in the latency gap between DRAM and block storage, and the patent activity tracked here follows the software and system-level problems that gap creates: byte addressability, write endurance management, crash consistency after a power failure, and the tiering software that decides what data lives where. The search spans 2015 through the 2026 cut-off and pulls 139 published families built around those exact technical claim terms rather than a broad memory-technology keyword.
Because publication typically lags filing by around 18 months, the last one or two years in any trend chart will always understate real filing activity — treat the most recent bars as a floor, not a ceiling.
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Filing trend and technology composition
Two views of the same 139 families: when the claims were filed, and which IPC subclasses they were built under.
A peak in 2019, then a decline
Filings ran from 13 in 2017 to a peak of 29 in 2019, then fell back toward single digits by the 2022 midpoint (4) and stayed flat or declining into the most recent complete years. That shape reads as a technology whose core claim space was staked out early in the storage-class-memory era, with later entrants filing narrower, more defensive follow-on claims rather than new foundational ones.
G06F dominates; device-level codes are secondary
Every one of the 139 records is classified under G06F (electric digital data processing), with G11C (static and digital memories) appearing in 20 and H04L (digital information transmission) in 11. Device-manufacture codes such as H10B and H01L appear in single digits, confirming that this corpus is about how systems manage persistent memory rather than how the memory cells themselves are built.
Shares are the percentage of the 139 records in scope. A patent can carry several IPC classes, so the shares add up to more than 100%.
Go deeper on Storage Class Memory and Persistent Memory with Eureka
This page is one run against one query. Ask Eureka your own question about storage class memory and persistent memory and every answer comes back with the patent numbers behind it.
Try EurekaThe most-cited records in this landscape
System and method for persistent memory rotation based on remaining write endurance
During a power-on self-test, the BIOS of an information handling system reads a percentage remaining of a persistent memory device. If the percentage remaining satisfies a threshold, the BIOS provides a replacement message or automatically swaps namespaces between two sets of persistent memory devices based on the write endurance remaining threshold.Filed by DELL PRODUCTS, LP; published 2022-01-11 as US11221766B2.
| # | Publication no. | Patent title | Citations |
|---|---|---|---|
| 1 | US20180260324A1 | Data Structure Store in Persistent Memory | 74 |
| 2 | US20150006834A1 | Method and apparatus for store durability and ordering in a persistent memory architecture | 69 |
| 3 | US20160342487A1 | High performance persistent memory | 63 |
| 4 | US10817502B2 | Persistent memory management | 55 |
| 5 | US20140317336A1 | Local direct storage class memory access | 44 |
| 6 | US20100106754A1 | Hardware and Operating System Support for Persistent Memory On A Memory Bus | 41 |
| 7 | US20140351535A1 | Snapshots and versioning of transactional storage class memory | 40 |
| 8 | US10733110B1 | Collecting statistics for persistent memory | 39 |
| 9 | US20170046268A1 | Write Mirroring to Storage Class Memory Devices | 38 |
| 10 | US20160253123A1 | NVMM: An Extremely Large, Logically Unified, Sequentially Consistent Main-Memory System | 37 |
Citation counts inside a searched corpus skew toward older, earlier-filed records simply because they have had more time to accumulate citations — read this as a signal of influence on the field, not of current commercial importance.
Each row carries its publication number; clicking a row searches Eureka by that number.
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Browse MCP servers →What the numbers mean for a filing decision
Three patterns in the data matter more than the raw counts on their own.
The foundational window has closed
The run-up to 29 filings in 2019 followed by a drop to 4 at the 2022 midpoint suggests the core architectural claims — byte-addressable access paths, basic crash-consistency schemes — were largely filed during the first wave. New entrants now face a denser prior-art floor for anything resembling those baseline mechanisms.
This is a US prosecution story
With 123 of 139 published records filed in the United States and the next largest office (China) at only 8, competitive and freedom-to-operate analysis for this technology should be anchored on USPTO prosecution first, then treated as a check elsewhere.
Software and controller logic outweighs device physics
Every record sits under G06F while only 20 also carry G11C and 6 carry H10B, meaning the bulk of active claim territory is in how software and controllers manage persistent memory rather than in the memory cell or die itself.
Eureka can read the same corpus for gaps instead of for coverage: under-claimed branches adjacent to storage class memory and persistent memory, with the prior art for and against each one.
| Assignee | Co-assignee | Shared families |
|---|---|---|
| International Business Machines Corporation (IBM) | IBM (China) Company Limited | 1 |
| International Business Machines Corporation (IBM) | IBM ISRAEL SCI & TECH LTD | 1 |
Only two co-assignee pairs appear in the dataset, both involving IBM entities across jurisdictions, indicating this field is prosecuted almost entirely by single-owner filings rather than joint ventures or cross-licensed development.
Who is filing, and where the gaps sit
Recent-year momentum has stalled across every tracked assignee, with each showing zero filings in the latest year — consistent with the broader post-2019 decline rather than any single company pulling back.
No assignee is currently accelerating
Every assignee with meaningful filing history in this set, from IBM to Rambus to Western Digital, shows zero filings in the most recent year. Given the publication lag, this likely reflects the broader slowdown rather than a genuine stop in R&D.
Ownership is fragmented, not pooled
With only two co-assignee pairs across the whole dataset, most families are prosecuted by a single owner. That makes freedom-to-operate clearance more tractable — there are fewer joint-ownership chains to trace — but also means licensing consolidation has not happened yet.
Influence sits with the earliest filers
The most-cited records in this set date to the mid-2010s, when the foundational architecture and durability-ordering claims were laid down. Newer filings have not yet had time to accumulate comparable citation counts, so treat the citation table as historical influence rather than a current importance ranking.
| Assignee | Recent year | YoY |
|---|---|---|
| Netlist, Inc. | 0 | — |
| International Business Machines Corporation (IBM) | 0 | — |
| Oracle International Corporation | 0 | — |
| Rambus Inc. | 0 | — |
| WOLLEY INC | 0 | — |
| Western Digital Technologies, Inc. | 0 | — |
| Intel Corporation | 0 | — |
| Tsinghua University | 0 | — |
Where to take this analysis
The dataset points to a mature, US-centred claim landscape with a narrowing window for foundational filings and a handful of specific under-claimed branches still open.
Map claims against the 2019 filing peak
Pull the granted claims from the highest-cited 2015–2019 records to see exactly which architectural elements are already blocked before drafting new claims in the same space.
Explore in Eureka →Check the under-claimed branches directly
Run a focused search against tiering-software heuristics and namespace-level endurance rotation to see how thin the prior art really is before committing drafting time.
Explore in Eureka →Common questions about storage class memory patents
This dataset defines storage class memory and persistent memory through the specific technical terms that appear in the claims and descriptions: byte addressability, write endurance, crash consistency, latency gap, and tiering software. It is filtered against IPC codes G11C13, G06F12 and G06F3, which cover static memory, memory-management architecture and input/output storage respectively. That combination captures system- and software-level patents about managing persistent memory rather than patents purely about the underlying memory cell physics.
The recent-year momentum data shows a set of established computing and memory companies with filing history in this space, including IBM, Oracle, Rambus, Western Digital and Netlist, alongside co-assignee activity involving IBM's regional entities. All of the assignees tracked for recent-year momentum show zero filings in the latest year, which is consistent with the dataset's overall post-2019 decline rather than a single company's withdrawal. For a current ranking, the assignee table on this page reflects family counts across the full 2015–2026 window.
Filings rose to a peak of 29 in 2019 from 13 in 2017, then fell to 4 by the 2022 midpoint and stayed flat or declining afterward. This pattern typically means the foundational architectural claims — basic byte-addressable access schemes, first-generation crash-consistency mechanisms — were filed early, leaving later entrants to file narrower, more defensive claims against an increasingly dense prior-art base. It also coincides with commercial storage-class-memory products like early persistent memory modules reaching the market, after which patenting activity commonly shifts from broad architecture to specific implementation detail.
The clearest under-claimed areas relative to the core write-endurance and crash-consistency claims are tiering-software heuristics for mixed DRAM/SCM pools, namespace-level write-endurance rotation schemes that go beyond BIOS-triggered swapping, dedicated crash-consistency verification tooling, and byte-addressable access APIs built for AI or accelerator workloads. These are inferred from the relative thinness of filings in adjacent IPC codes like G06N and H03M compared to the dense core under G06F and G11C. A first claim in any of these areas would need to specify the triggering condition, the data structure affected and the recovery or verification mechanism precisely enough to distinguish it from the existing BIOS- and controller-level art.
No — the filing trend is flat to declining, not growing. After peaking at 29 families in 2019, activity dropped to 4 by the 2022 midpoint, and every tracked assignee shows zero filings in the most recent year. Because publication lags filing by roughly 18 months, the very last year or two in any chart will understate true activity, but even accounting for that lag the multi-year trend points downward rather than toward renewed growth.
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Disclaimer. This page is generated from Patsnap Eureka data drawn from a limited snapshot of global patent and scientific-literature records, and is provided for general information and reference only.
Patent data carries inherent limitations: recent filings (typically the most recent 18–24 months) are under-counted due to standard publication lag; counts may be reported at either a patent-family or a patent-record basis and are not always directly comparable; classification, applicant-name, and citation data may contain errors, duplicates, or omissions; and the underlying search query defines and constrains the scope shown. As a result, the analysis may be incomplete or inaccurate and may not reflect the full technology landscape.
Nothing on this page constitutes an exhaustive prior-art, novelty, freedom-to-operate, or validity search, nor does it constitute legal, financial, investment, or professional advice, and it should not be relied upon as such. Any patent, commercial, or strategic decision should be verified independently and reviewed with qualified patent, legal, and domain professionals. Patsnap makes no warranties, express or implied, as to the accuracy, completeness, or fitness for any particular purpose of the information presented.
Machine translation. Assignee and organisation names originally recorded in Chinese, Japanese or Korean have been rendered into English by an AI translation step so that the tables stay readable. These renderings are best-effort and may not match a company’s registered English name; the original name is what the underlying patent record carries, and it is what any Eureka query launched from this page uses.