Strained SiGe Channel Transistor Patents 2026 — PatSnap Eureka
Strained SiGe Channel Transistor Patents 2026
Compressively strained Ge/SiGe channels boost hole mobility 2–4× over relaxed silicon, making them the leading PMOS candidate below 22 nm. This dataset spans foundational 1999 filings through active 2026 GAA nanosheet patents.
Why Strained SiGe Channels Matter at Sub-22 nm Nodes
Strained SiGe channel technology exploits the approximately 4.2% lattice mismatch between silicon and germanium to induce biaxial or uniaxial stress in the transistor channel region. This stress splits valence or conduction band degeneracies, reduces carrier effective mass, and suppresses inter-valley scattering—collectively boosting hole mobility by 2–4× and electron mobility by 1.5–2× over relaxed silicon.
The field spans five interrelated sub-domains in this dataset: compressive SiGe/Ge channels for PMOS, embedded SiGe source/drain stressors, strain-relaxed buffers (SRBs), gate-all-around and nanosheet architectures, and tensile-strained Ge channels for CMOS. As IMEC notes, relaxed Ge channel devices do not outperform strained Si channel p-FinFETs—strained Ge is crucial to boost channel mobility.
The dataset spans more than two decades, from Micron Technology’s polycrystalline SiGe channel thin-film transistor filings in 1999 through IBM’s SiGe/Si dual-channel FET fabrication method filed in 2026. Core embedded-stressor mechanisms are mature, while gate-all-around nanosheet geometries with spatially graded Ge concentration profiles represent the active frontier.
In this dataset, 10 distinct assignees account for the majority of patent records. GlobalFoundries is the most prolific filer in this dataset with approximately 12 records, followed by Intel at approximately 10 and TSMC at approximately 8. The US jurisdiction appears in approximately 70% of retrieved patent records, followed by EP, GB, DE, SG, WO, and CN filings.
Filing Trends and Technology Cluster Distribution
The retrieved dataset reveals four major technology clusters spanning embedded stressors, SRB-based Ge channels, in-situ conversion, and GAA nanosheets. Filing activity spans 1999–2026, with the most recent filings concentrated in GAA nanosheet architectures.
Patent Records by Technology Cluster in This Dataset
Embedded SiGe source/drain stressors and SRB-based Ge channels together account for the largest share of records in this dataset, while GAA nanosheet filings represent the fastest-growing cluster in the 2022–2026 period.
↗ Click bars to exploreFiling Activity by Era in Retrieved Records
Filing activity in this dataset accelerated sharply in the 2008–2017 scaling era and remains active in the 2018–2026 advanced node era, with GAA and dual-channel FET patents as the dominant new claim categories.
↗ Click bars to exploreKey Application Areas for Strained SiGe Channel Technology
Retrieved patents and literature map strained SiGe channel technology across five application domains, from mainstream logic scaling at advanced nodes to high-frequency RF, bio-sensing, and radiation-hardened memory.
High-Performance Logic at Sub-22 nm
The dominant application in this dataset covers CMOS nodes from 90 nm down to sub-3 nm, where strained SiGe channels boost PMOS drive current and reduce supply voltage. Literature confirms that high-k/metal gate, strain engineering, and 3D FinFET were deployed together from 22 nm to 14 nm nodes. Key filers include TSMC, Intel, GlobalFoundries, IBM, Samsung, and IMEC.
Logic ScalingMobile and Low-Power Computing
Several Intel patents explicitly cite mobile device applications as motivation for SiGe channel conversion techniques, driven by the need for smaller die implementations. The conversion of Si FinFET fins to SiGe at low cost and high integration density is directly motivated by mobile SoC requirements, with filings spanning US, GB, and WO jurisdictions from 2014 to 2018.
Mobile / Low-PowerHigh-Frequency and RF/Microwave Electronics
Elpis Technologies (IBM lineage) filed Ge-channel heterostructure patents for high-speed low-noise microwave, submillimeter-wave, and millimeter-wave applications covering HEMT-compatible Ge channel structures in Si/SiGe stacks (2006–2007, US). Shanghai New Micro Technology R&D Center filed a silicon-based GeSn HEMT targeting 5G and high-frequency satellite communication (CN, 2020), extending the Ge-alloy channel concept to sub-THz RF applications.
RF / MicrowaveMemory and Radiation-Hardened Electronics
IBM applied the SiGe/Si heterojunction to single-transistor DRAM cell design, exploiting valence band offset between Si and SiGe to suppress source-body junction leakage. Literature from 2023 demonstrates radiation-hardened SRAM cells using germanium-based doping-less tunnel FETs (Ge DLTFET), confirming viability for space and harsh-environment electronics. Hewlett Packard Enterprise Development LP also filed patents on rounded 3D germanium active channels applicable to integrated sensing platforms (2011, US).
Memory / Radiation-HardLeading Assignees in Strained SiGe Channel Patents — Dataset Snapshot
In this dataset, GlobalFoundries and Intel are the two most prolific filers with approximately 12 and 10 records respectively in retrieved records, spanning process integration, defect mitigation, and channel conversion techniques across US, GB, DE, SG, and WO jurisdictions.
Top Assignees by Filing Count in Retrieved Records (Dataset Snapshot)
↗ Click bars to exploreGlobalFoundries U.S. Inc.
GlobalFoundries is the most prolific filer in this dataset with approximately 12 records spanning US, DE, GB, and SG jurisdictions, filed primarily from 2008 to 2014. Key patents cover embedded SiGe on double-buried-oxide SOI wafers (2008), silicide resistance reduction in Si/Ge drain/source regions (2010), defect rate reduction in PFET SiGe epitaxial growth (2011), and graded Ge concentration source/drain methods (2014). Filing focus is concentrated on process integration for high-volume manufacturing at advanced nodes.
United StatesIntel Corporation
Intel holds approximately 10 records in this dataset across US, GB, and WO jurisdictions, covering filings from 2007 to 2018. Core patents include epitaxial SiGe for reduced contact resistance (2007, US), multiple filings on conversion of thin transistor elements from silicon to silicon germanium (2014–2018, US/GB/WO), and a tensile-strained germanium channel transistor filed via WO in 2017. The Tahoe Research IP vehicle holds additional strained-channel source/drain stressor patents (2017–2018, US), indicating Intel’s broad strategic coverage across PMOS and NMOS Ge channel approaches.
United StatesFive Frontier Signals from 2022–2026 Filings
The most recent filings (2022–2026) in this dataset point toward five directional shifts: Ge-concentration engineering in GAA nanosheets, dual-channel CMOS co-integration via thermal oxidation condensation, inverted SiGe-cladding PMOS nanosheet architectures, ion-implantation-based FDSOI stressor formation, and GeSn alloy channels targeting terahertz and 6G RF applications.
Graded Ge Profiles in GAA Nanosheet Channels
IBM’s 2024 pending filing describes a strained nanosheet channel with a SiGe core layer and Si cladding layer; its 2025 filing reduces bandgap offset at source/drain–channel interfaces via geometric engineering of inner spacers. TSMC’s 2022 dual-channel GAA patent introduces spatially graded Ge concentration profiles within nanosheet middle sections, enabling simultaneous strain and electrostatics optimization. These filings position Ge-concentration engineering as a first-class design variable at the 2 nm node and below.
Ion Implantation SiGe Stressor for FDSOI PFET
Applied Materials’ 2023 filing discloses forming SiGe stressors in FDSOI PFET devices via germanium ion implantation into the channel layer to greater than 40% Ge concentration and subsequent recrystallization. This implant-based approach avoids selective epitaxial growth complexity in FDSOI flows. The approach represents a cost-effective alternative for RF and IoT device applications on FDSOI platforms.
Embedded SiGe Stressors vs. SRB-Based Compressive Ge Channels
Click any row to explore further.
| Dimension | Embedded SiGe Source/Drain Stressors | SRB-Based Compressive Ge/SiGe Channels |
|---|---|---|
| Compressive uniaxial stress from SiGe lattice mismatch in recessed S/D cavities | Biaxial compressive strain from fully strained Ge/SiGe layer grown above SiGe SRB on Si | N/A |
| Moderate — limited by alloy Ge content and cavity geometry | High — decoupled from substrate, enables near-pure Ge channel strain levels | N/A |
| Foundational from 90 nm node; used through FinFET era | Primary approach for sub-22 nm PMOS FinFET and GAA devices | N/A |
| TSMC (2004–2022), GlobalFoundries (2008–2014), Intel (2007–2009), Samsung (2014–2018) | IMEC VZW (2016–2024), CEA (2022–2023), IBM (2017–2026) | N/A |
| Lower — compatible with standard CMOS epitaxial flows; SiGe grown in recessed S/D only | Higher — requires SRB growth, virtual substrate, and precise Ge content grading | N/A |
| Managed via graded Ge profiles and cap layers (GlobalFoundries 2011, 2014 patents) | Requires careful SRB grading to prevent dislocation propagation into channel | N/A |
| Significant — primary mechanism for PMOS performance at 90–28 nm | 2–4× hole mobility gain over relaxed silicon confirmed in IMEC literature | N/A |
| ~16 records — largest cluster in retrieved records | ~10 records — second largest cluster in retrieved records | N/A |
Frequently Asked Questions: Strained SiGe Channel Transistors
IMEC’s research confirms that relaxed Ge channel devices do not outperform strained Si channel p-FinFETs. Strained Ge is crucial to boost channel mobility because the compressive strain splits valence band degeneracies, reduces hole effective mass, and suppresses scattering—delivering 2–4× hole mobility gain over relaxed silicon.
A SRB is a graded or virtual SiGe substrate grown on silicon that allows a fully strained Ge or high-Ge-content SiGe channel layer to be deposited above it. It decouples strain control from the underlying Si substrate choice, enabling higher strain levels than embedded stressors alone—particularly useful for sub-22 nm PMOS FinFET and GAA devices, as demonstrated in IMEC’s patent filings from 2016 to 2024.
Intel’s approach deposits a Ge-containing cladding layer on an existing Si fin and anneals it to drive Ge diffusion into the channel body, converting Si FinFET fins to SiGe in situ. This avoids full epi stack redesign. Intel’s patent family covers US, GB, and WO (PCT) jurisdictions, with filings spanning 2014 to 2018, and a related WO filing under inventor Anand S. Murthy (2014).
IBM’s 2024 filing describes a strained nanosheet with SiGe core and Si cladding; its 2025 filing addresses bandgap offset reduction at source/drain–channel interfaces via inner spacer geometry. TSMC’s 2022 dual-channel GAA patent introduces spatially graded Ge concentration profiles within nanosheet middle sections. IBM’s 2026 filing describes SiGe/Si dual-channel FET fabrication via sequential oxide deposition and thermal annealing.
In this dataset, GlobalFoundries holds approximately 12 records (US, DE, GB, SG), Intel approximately 10 (US, GB, WO), TSMC approximately 8 (US, SG), IBM/Elpis Technologies approximately 7 (US), and Infineon Technologies AG approximately 5 (US, DE). The US jurisdiction appears in approximately 70% of retrieved patent records.
GeSn alloy channels combine germanium with tin to further reduce the bandgap and increase carrier mobility beyond binary SiGe. Two CN filings from Shanghai New Micro Technology R&D Center (2019–2020) describe silicon-based GeSn HEMT structures targeting 5G and high-frequency satellite communication. A 2026 CN filing from the Institute of Metals Research, Chinese Academy of Sciences describes a Si/graphene/Ge barristor transistor array for terahertz-range applications.
Data and insights on this page are based on a limited patent and literature dataset and are for reference only. Figures may not represent the complete technology landscape.