Strained Silicon Channel Engineering 2nm — PatSnap Eureka
Strained Silicon Channel Engineering for Carrier Mobility in Nanosheet FETs at 2nm
At the 2nm node, strained silicon channel engineering has become the primary carrier mobility enabler in gate-all-around nanosheet FETs — combining valley engineering, quantum confinement, and Type-II band alignment to deliver extraordinary performance gains. Explore the patents and physics driving this frontier.
Mobility Improvement by Strain Approach
Key performance metrics from patent and literature corpus
Source: PatSnap Eureka · Patent & literature corpus · 2015–2023
Band Splitting, Quantum Confinement, and Valley Engineering
The performance gains delivered by strained silicon channel engineering at the 2nm node rest on three coupled physical mechanisms: strain-induced band splitting, quantum confinement in ultra-thin bodies, and valley engineering. At channel thicknesses approaching 2–3 nm, strain is not merely additive but multiplicatively synergistic with quantum confinement — a finding with direct implications for GAA nanosheet FET design.
Research from the School of Electrical Engineering at KAIST demonstrated that combining high tensile strain with extremely well-controlled silicon surface roughness in a 2.5 nm thick silicon channel achieved a device mobility increase of approximately 500% through valley engineering — defined as the deliberate lifting of degeneracy between conduction band valleys via strain-induced band splitting and quantum confinement effects.
According to IBM's 2023 patent on nanosheet transistors with strained channel regions, incorporating strain into the FET channel stretches the crystal lattice, reducing scattering and increasing carrier velocity. IBM's sustained series of divisional filings from 2019 through 2023 confirms that SiGe/Si multilayer stacks introduce strain at the SiGe-Si interface, with the strain state of the released Si channel determined by the Ge concentration and the thickness of the surrounding sacrificial SiGe layers during the channel-release step. This is consistent with broader IEEE-published research on band engineering at advanced nodes.
The transverse strain variant — described in IBM's 2021 patent on nanosheet transistors with transverse strained channel regions — deposits a strained material along the sidewall surface of the gate structure to introduce lateral stress components into nanosheet channel layers. This geometry is particularly relevant for narrow-width nanosheets where edge stress contributions are significant, and allows strain to be introduced after the channel-release step, decoupling the strain budget from the constraints of the epitaxial growth sequence. PatSnap's IP analytics platform enables landscape analysis of these IBM divisional filing clusters to map freedom-to-operate risk.
Patent Landscape & Performance Benchmarks
Quantitative insights from the strained silicon nanosheet FET patent and literature corpus, analysed via PatSnap Eureka.
IBM Strained Nanosheet Channel Patent Filings (2019–2023)
IBM's sustained divisional filing strategy demonstrates dominant IP position in strained GAA nanosheet channel engineering.
Dominant Technical Approaches in Strained Nanosheet FET Patents
Four primary strain engineering strategies identified across the corpus, each addressing distinct aspects of carrier mobility enhancement.
Process Integration Challenges vs. Performance Impact at 2nm
Key process integration steps identified across the corpus and their relative impact on delivered channel strain and device performance.
Tri-Layer Heterostructures, Type-II Band Alignment, and Crystal Orientation
Beyond simple biaxial strain, researchers have developed multi-layer heterostructures and orientation-specific designs to simultaneously harness quantum well confinement and quasi-ballistic transport.
Tri-Layered s-Si/s-SiGe/s-Si with Type-II Band Alignment
Work from NIT Mizoram describes the first implementation of a cylindrical GAA FET with a tri-layered s-Si/s-SiGe/s-Si channel at 10 nm gate length. The two s-Si wells surrounding the s-SiGe barrier create a two-dimensional charge centroid through electrostatic potential differences, improving carrier mobility, current density, and transconductance in alignment with the IRDS 2022 3nm technology node roadmap.
Quasi-ballistic transport enabledCompressive SiGe Barrier Inducing Tensile Strain in Si Layers
A cylindrical nanowire system with an ultra-thin s-Si outer layer, s-SiGe middle layer, and s-Si inner layer uses the compressively strained SiGe barrier to induce tensile strain in both surrounding Si layers, creating quantum-well-barrier structures with Type-II band alignment. The quantum-well formed by congealing the channel with the strained layers enables carrier confinement and quasi-ballistic transport, improving carrier mobility and countering threshold voltage roll-off.
Threshold voltage roll-off mitigated<100> for NMOS, <110> for PMOS — Independent Mobility Optimisation
IBM's patents on channel orientation of CMOS gate-all-around FET devices establish that electron mobility is maximized on the <100> crystal surface orientation while hole mobility is maximized on the <110> orientation. By independently configuring the channel orientation of N-type and P-type nanosheet FET devices within a CMOS layout, both device types can simultaneously achieve peak carrier mobility without requiring additional process steps. PatSnap Analytics can map the FTO landscape around this IBM IP cluster.
No additional masking requiredFour-Gate Tri-Layered HOI Channel for Biaxial Quantum Confinement
A gate-all-around FET with four gates surrounding the tri-layered channel demonstrates mobility increase due to quantum tunneling phenomenon and ballistic behavior in the tri-layered strained channel at 22 nm and 10 nm channel lengths. The system employs biaxial strain induced by the s-SiGe middle layer to confine carriers at multiple quantum states simultaneously, directly targeting 2nm-class technology requirements. PatSnap's materials intelligence covers the SiGe epitaxy literature underpinning this approach.
Multi-quantum-state confinementStressor Retention, S/D Trimming, and Inner Spacer Engineering
Delivering theoretical mobility benefits to manufactured 2nm-class devices requires careful process integration — epitaxial stressors can be partially or fully relaxed during release and gate-formation steps.
S/D Trimming for Stressor Retention
Shanghai ICMIC demonstrated that a new S/D trimming process for GAA nanosheet transistors, optimized to retain channel stress from epitaxial S/D stressors, achieved up to 27.8% improvement in 7-stage ring oscillator delay for 3-layer stacked GAA devices while also enabling more than 4-layer vertical nanosheet stacking for technology extension beyond 3nm. This directly links stressor-preservation process design to circuit-level performance metrics.
Inner Spacer Geometry and Elastic Stiffness
Research from Chungbuk National University demonstrated through 3D simulation that inner spacer geometry and elastic properties directly affect the mechanical stability of suspended nanosheets during channel release. Rigid dielectric materials and wide contact areas between the inner spacer and nanosheet are preferred to prevent deformation that could alter the designed strain state — a critical constraint for preserving engineered mobility gains through the replacement gate process.
Key Players and Patent Positions in Strained Nanosheet FET Engineering
The corpus reveals a concentrated set of contributors spanning dominant patent filers, process integration leaders, and academic innovators whose work defines the 2nm frontier.
| Organisation | Primary Contribution | Key Filing / Publication | Technology Focus |
|---|---|---|---|
| IBM | Dominant patent filer — strained channel regions, transverse strain, crystal orientation | 4+ active US filings (2019–2023); 2 crystal orientation filings | Gate-sidewall strained material deposition; SiGe/Si multilayer stack |
| Applied Materials | Process integration IP for contact resistance reduction in nanosheet FETs | Multi-jurisdictional filings: US, WO, KR, JP (2022) | Selective silicidation; wrap-around metal fill contacts |
| GlobalFoundries | Strained silicon carbide NMOS channel technology | SiC channel patent (2015) — (110) substrate | Carbon implant / epitaxial SiC for NMOS electron mobility |
| KAIST | Valley engineering physics — ~500% mobility improvement at 2.5 nm | Literature: Valley-engineered ultra-thin silicon (2016) | Tensile strain + surface roughness control in junctionless transistors |
| Shanghai ICMIC | S/D trimming for stressor retention — 27.8% RO delay improvement | Literature: S/D Trimming GAA Nanosheet (2022) | Stressor-preserving trimming; 4+ layer nanosheet stacking |
Track all active filers in strained nanosheet FET engineering
PatSnap Eureka monitors new filings, divisionals, and citations across IBM, Applied Materials, GlobalFoundries, and academic institutions in real time.
What the Patent and Literature Corpus Tells Us About 2nm Strained Channels
The transition to gate-all-around nanosheet FET architectures at the 2nm node has elevated strained silicon channel engineering from a supplementary technique to a primary carrier mobility enabler. The corpus identifies four dominant technical approaches: SiGe/Si multilayer sacrificial-channel stacks, strained material deposition along gate sidewalls, crystal orientation engineering of NMOS and PMOS channels, and tri-layered s-Si/s-SiGe/s-Si heterostructures combining quantum well confinement with Type-II band alignment.
IBM holds the dominant patent position, with a sustained series of divisional filings from 2019 through 2023. Applied Materials leads process integration IP for contact resistance reduction across multiple jurisdictions. PatSnap customers in semiconductor R&D use Eureka to navigate this dense IP environment and identify freedom-to-operate paths.
The Semiconductor Industry Association and NIST have both identified GAA nanosheet FETs as central to the US semiconductor roadmap, making freedom-to-operate analysis in this space a critical priority for any fab or fabless design team targeting sub-3nm nodes. The PatSnap platform provides the global patent coverage needed for this analysis.
Source/drain trimming optimized for stressor retention and inner spacer engineering with rigid dielectric materials are identified as the two most critical process integration levers for preserving designed strain states through to manufactured devices — directly linking process choices to the 27.8% ring oscillator delay improvement demonstrated by Shanghai ICMIC.
Strained Silicon Channel Engineering at 2nm — Key Questions Answered
Incorporating strain into the FET channel stretches the crystal lattice, reducing scattering and increasing carrier velocity. At channel thicknesses approaching 2–3 nm, strain is not merely additive but multiplicatively synergistic with quantum confinement, enabling extraordinary mobility gains through valley engineering — the deliberate lifting of degeneracy between conduction band valleys via strain-induced band splitting and quantum confinement effects.
Research from KAIST found that combining high tensile strain with extremely well-controlled silicon surface roughness in a 2.5 nm thick silicon channel achieved a device mobility increase of approximately 500% through valley engineering.
A tri-layered s-Si/s-SiGe/s-Si heterostructure consists of an ultra-thin s-Si outer layer, s-SiGe middle layer, and s-Si inner layer, where the compressively strained SiGe barrier induces tensile strain in both surrounding Si layers, creating quantum-well-barrier structures with Type-II band alignment. This enables carrier confinement and quasi-ballistic transport, improving carrier mobility and countering threshold voltage roll-off.
Electron mobility is maximized on the <100> crystal surface orientation while hole mobility is maximized on the <110> orientation. By independently configuring the channel orientation of N-type and P-type nanosheet FET devices within a CMOS layout, both device types can simultaneously achieve peak carrier mobility — a technique that complements strain engineering without requiring additional process steps.
A new S/D trimming process for GAA nanosheet transistors, optimized to retain channel stress from epitaxial S/D stressors, achieved up to 27.8% improvement in 7-stage ring oscillator delay for 3-layer stacked GAA devices while also enabling more than 4-layer vertical nanosheet stacking for technology extension beyond 3nm.
Inner spacer geometry and elastic properties directly affect the mechanical stability of suspended nanosheets during channel release. Rigid dielectric materials and wide contact areas between the inner spacer and nanosheet are preferred to prevent deformation that could alter the designed strain state.
Still have questions about strained silicon channel engineering? Let PatSnap Eureka search the patent and literature corpus for you.
Ask PatSnap Eureka Your R&D QuestionAccelerate Your 2nm Nanosheet FET Research with AI-Powered Patent Intelligence
Join 18,000+ innovators already using PatSnap Eureka to navigate complex IP landscapes, identify white-space opportunities, and validate strain engineering strategies at advanced technology nodes.
References
- Valley-engineered ultra-thin silicon for high-performance junctionless transistors — School of Electrical Engineering, KAIST, 2016
- Nanosheet transistors with strained channel regions — International Business Machines Corporation, 2023
- Nanosheet transistors with strained channel regions — International Business Machines Corporation, 2021
- Nanosheet transistors with strained channel regions — International Business Machines Corporation, 2020
- Nanosheet transistors with transverse strained channel regions — International Business Machines Corporation, 2021
- Channel orientation of CMOS gate-all-around field-effect transistor devices for enhanced carrier mobility — IBM, 2020
- Channel orientation of CMOS gate-all-around field-effect transistor devices for enhanced carrier mobility — IBM, 2021
- Evolution of type-II hetero-strain cylindrical-gate-all-around nanowire FET — National Institute of Technology Mizoram, 2023
- A nanowire system for faster switching with enhanced on-current and its preparing process thereof — Rasmita Barik, 2023
- A nano-device using ultra-thin tri-layered strained-channel for enhancing drive currents in tri-gate Fin-FET architecture — Rasmita Barik, 2023
- A nanosystem-based device using ultra-thin tri-layered HOI channel with increased drive currents in rectangular gate — Kuleen Kumar, 2023
- Source/Drain Trimming Process to Improve Gate-All-Around Nanosheet Transistors Switching Performance and Enable More Stacks of Nanosheets — Shanghai ICMIC, 2022
- Process integration to reduce contact resistance in semiconductor device — Applied Materials, Inc., US, 2022
- Process integration to reduce contact resistance in semiconductor device — Applied Materials, Inc., WO, 2022
- A Review of the Gate-All-Around Nanosheet FET Process Opportunities — IBM Research Albany, 2022
- Inner Spacer Engineering to Improve Mechanical Stability in Channel-Release Process of Nanosheet FETs — Chungbuk National University, 2021
- Strained silicon carbide channel for electron mobility of NMOS — GlobalFoundries Inc., 2015
- IEEE — Institute of Electrical and Electronics Engineers (contextual reference for band engineering literature)
- Semiconductor Industry Association — US semiconductor roadmap and GAA FET technology priorities
- National Institute of Standards and Technology (NIST) — semiconductor metrology and advanced node standards
All data and statistics on this page are sourced from the references above and from PatSnap's proprietary innovation intelligence platform.
PatSnap Eureka searches patents and research to answer instantly.