Overlay accuracy — the precise alignment of successive patterned layers on a wafer — is widely recognised as one of the most demanding constraints in advanced node semiconductor manufacturing. As ASML reported from production data, matched-machine overlay reached 1.1 nm for 0.33 NA EUV systems targeting the 5 nm logic node, and the roadmap for high-NA EUV (NA ≥ 0.55) pushes requirements well below 1 nm, into the sub-angstrom regime for the most critical layers.

The engineering challenge is therefore not a single bottleneck but a system-level problem coupling optics, mechanics, metrology, thermal management, and computational control. The dataset underpinning this analysis comprises more than 50 patents and literature sources spanning assignees including Samsung Electronics, ASML, Carl Zeiss SMT, IMEC, KLA-Tencor, Applied Materials, TSMC, and academic institutions including Delft University of Technology and Physikalisch-Technische Bundesanstalt.

The dominant technical themes are: overlay error detection and correction in multi-layer EUV exposure, optical system stability and mirror performance, illumination uniformity control, high-NA scanner design with pellicle integration, and mask metrology at actinic wavelengths. Each of these dimensions contributes independently to the overlay error budget — and sub-angstrom targets require simultaneous near-elimination of all contributors. Learn how PatSnap IP Analytics maps innovation across these dimensions.

Full-wafer CD uniformity below 0.5 nm has already been achieved at 0.33 NA — itself a data point that illustrates how tightly all subsystems must be controlled to approach the sub-angstrom overlay target for subsequent nodes, per advanced materials and process research tracked in the PatSnap platform.

Beyond optics, overlay error in EUV scanners originates in the relative positioning of the reticle stage and wafer stage during scanning exposure. At sub-angstrom overlay targets, the control system must resolve and compensate for vibration, thermomechanical drift, air-bearing nonlinearity, and inter-field systematic errors — all simultaneously and within the exposure timescale.

Samsung Electronics holds a substantial IP position in overlay correction methodology for EUV. Their 2021 patent describes a control unit that corrects a first overlay parameter by leveraging a measured correlation with a second overlay parameter — effectively using cross-parameter relationships to infer and correct errors that cannot be directly measured in-line during exposure. A 2026 continuation refines this parameter-correlation correction scheme to extend the framework to future-generation scanner architectures.

The problem is compounded in mixed-technology fabs where both DUV and EUV scanners are used on the same wafer stack. Machine-to-machine overlay matching — which ASML reported at 1.1 nm across a fleet of 0.33 NA tools — must be tightened by nearly an order of magnitude for the sub-angstrom targets of high-NA EUV nodes. Explore how PatSnap IP Analytics tracks these cross-platform overlay challenges.

TNO Netherlands has described an innovative approach using acoustic force microscopy to directly measure sub-surface overlay between patterned device layers. This is significant because conventional optical overlay marks may not resolve the true device-layer registration at the angstrom scale — direct atomic-force-based measurement of buried structures can validate or supplement scanner-based correction data. The NIST metrology framework for nanoscale measurement underpins the uncertainty budgets applied in such approaches.