Substrate Surface Finish Patents: Top Companies & Trends 2026
- 38.5% of all 4,149 records sit with just five assignees, with the leader alone holding 485 records — this field is concentrated, not fragmented.
- Filings peaked in 2023 at 372 then eased from 284 (2021) to 229 (2024), a 19% pullback that predates the still-incomplete 2025–2026 data.
- H01L and H05K overlap on 63.9% and 43.0% of records respectively, while coating and surface-deposition claims (C23C) cover only 1.7% — a visibly thinner branch.
Filing growth compares 2021 (284 records) with 2024 (229) — a three-year span. 2024 is the most recent year we treat as complete: publication lags filing by roughly 18 months, so 2025 onwards are still filling in and any growth rate that ends there would understate the field. Top-5 share is the combined record count of the five largest assignees divided by all 4,149 records in scope (CR5), not by the ranked leaders only.
What this landscape covers
This landscape tracks patent filings on substrate surface finish and solder resist technology: solder mask and solder mask defined (SMD) versus non-solder mask defined (NSMD) pad structures, electroless nickel immersion gold and related finishes, photoimageable dielectric layers, and the defect modes tied to them — black pad defect, thermal cycling cracks and resist adhesion failure. These are the process and structural choices that determine whether a packaging substrate survives assembly and field reliability testing.
The scope draws on 4,149 published records filed between 2015 and the July 2026 data cut-off, classified predominantly under semiconductor device (H01L) and printed circuit (H05K) codes, with smaller but distinct clusters in photolithography, antenna integration and surface coating classes.
Filing trends and technology composition
The dataset spans 4,149 published records from 2015 through the July 2026 data cut-off, giving a decade-plus view of how solder resist and surface-finish claims have moved across semiconductor packaging and printed-circuit filings.
Filing activity climbed through the early 2020s
Annual filings rose from 153 in 2017 to a peak of 372 in 2023. Filings fell from 284 in 2021 to 229 in 2024, a 19% decline over that three-year span; years after 2024 are still incomplete because publication typically lags filing by around 18 months, so the most recent bars should be read as a floor, not a final count.
H01L and H05K dominate the classification spread
Semiconductor devices (H01L) appear on 63.9% of the 4,149 records and printed circuits and assemblies (H05K) on 43.0%, with the two overlapping heavily on the same substrate filings. Smaller classes such as photolithography (G03F, 3.6%) and coating/surface deposition (C23C, 1.7%) show far less claim density, marking them as narrower, less-contested branches of the same field.
Shares are the percentage of the 4,149 records in scope. A patent can carry several IPC classes, so the shares add up to more than 100%.
Go deeper on Substrate Surface Finish and Solder Resist with Eureka
This page is one run against one query. Ask Eureka your own question about substrate surface finish and solder resist and every answer comes back with the patent numbers behind it.
Try EurekaThe patents shaping this field
US8232641B2 — Wiring substrate and semiconductor device having connection pads formed in non-solder mask defined structure
A wiring substrate includes a semiconductor chip on which a plurality of bumps are mounted, and a plurality of connection pads joined to the bumps in a flip-chip method. Connection pads in the peripheral portion of the substrate are formed in a non-solder mask defined structure, while connection pads in the center portion are formed in a solder mask defined structure.Filed by Shinko Electric Industries, granted 2012-07-31 — a mixed-zone pad-definition claim that sits inside the H01L class covering 63.9% of records in scope.
| # | Publication no. | Patent title | Citations |
|---|---|---|---|
| 1 | JP1990016765B2 | JP1990016765B2 | 669 |
| 2 | US6048755A | Method for fabricating BGA package using substrate with patterned solder mask open in die attach area | 483 |
| 3 | US20180055529A1 | Ultrasonic transducer techniques for ultrasonic surgical instrument | 315 |
| 4 | US20080246136A1 | Chips having rear contacts connected by through vias to front contacts | 305 |
| 5 | US6034427A | Ball grid array structure and method for packaging an integrated circuit chip | 299 |
| 6 | US6150193A | RF shielded device | 290 |
| 7 | US5872399A | Solder ball land metal structure of ball grid semiconductor package | 286 |
| 8 | US5981314A | Near chip size integrated circuit package | 282 |
| 9 | US5716663A | Multilayer printed circuit | 265 |
| 10 | US6379745B1 | Low temperature method and compositions for producing electrical conductors | 257 |
Ranked by citation count within the searched corpus; older records accumulate citations over more years, so treat this as a measure of influence rather than current relevance.
Each row carries its publication number; clicking a row searches Eureka by that number.
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Browse MCP servers →What the filing pattern signals
Three patterns stand out once record counts, classification shares and citation weight are laid side by side: concentration at the top of the assignee table, a plateau rather than a collapse in recent filing volume, and a technology mix still anchored in pad-geometry claims.
Ownership sits with a small group
The leading assignee alone holds 485 records, and the top ten combined account for 51.4% of all 4,149 records in scope. That leaves a long tail of smaller filers holding the remaining share, which matters for licensing and freedom-to-operate scoping — start with the concentrated group before widening the search.
A pullback from the 2023 peak, not a collapse
Filing volume climbed steadily to a peak of 372 records in 2023 before easing to 229 by 2024. The -19% move across 2021–2024 is a real signal; the further drop shown for 2025–2026 is not, since publication lag of roughly 18 months means those years are still filling in.
Pad geometry dominates over finish chemistry
Semiconductor device claims (H01L) and printed-circuit claims (H05K) cover the large majority of records at 63.9% and 43.0% respectively, while coating and surface-deposition claims (C23C) sit at just 1.7%. That gap suggests structural pad-definition claims have absorbed far more filing activity than finish-chemistry claims to date.
Eureka can read the same corpus for gaps instead of for coverage: under-claimed branches adjacent to substrate surface finish and solder resist, with the prior art for and against each one.
| Assignee | Co-assignee | Shared families |
|---|---|---|
| AT & S Austria Technologie & Systemtechnik AG | AT & S (China) Co., Ltd. | 2 |
| AT & S Austria Technologie & Systemtechnik AG | WEIDINGER GERALD | 1 |
| AT & S Austria Technologie & Systemtechnik AG | STAHR JOHANNES | 1 |
| AT & S Austria Technologie & Systemtechnik AG | MAYR GÜNTHER | 1 |
| AT & S Austria Technologie & Systemtechnik AG | ALOTHMAN ALTERKAWI AHMAD BADER | 1 |
| Intel Corporation | THOMAS THOMAS P | 1 |
| Intel Corporation | SUBBAREDDY DHEERAJ | 1 |
| Intel Corporation | PANG MENGZHI | 1 |
Co-assignment activity in this dataset is thin — ten identified pairs in total, with the strongest pairing linked to only two shared records — indicating that most substrate finish and solder resist work is filed independently rather than through joint ventures or shared R&D arrangements.
Who is filing, and where the field is still open
The assignee ranking covers 100 companies, counted by patent family, out of the 4,149 records in scope. Filing is concentrated at the top, but recent-year momentum shows even large filers pulling back, and several structurally adjacent branches remain thin.
A clear leader, not a crowded top tier
The leading assignee's 485 records compare to 212 for the fifth-ranked and 92 for the tenth-ranked filer, a steep drop-off that marks a genuine leader rather than a tightly bunched top group.
Latest-year filings are down across the leading group
Several of the largest historical filers show sharp year-over-year declines in latest-year filing counts, from -85% to -100% among some of the top names, though this partly reflects the 18-month publication lag rather than a confirmed strategic pullback.
Filing is US-weighted but genuinely global
The United States receives the largest single share of filings at 2,160, with Europe, Japan, Taiwan, WIPO and China each contributing meaningful volume — evidence that solder resist and surface-finish claims are prosecuted across the full packaging supply chain, not just in one jurisdiction.
| Assignee | Recent year | YoY |
|---|---|---|
| Samsung Electronics Co., Ltd. | 5 | -85% |
| AT & S Austria Technologie & Systemtechnik AG | 4 | -91% |
| Advanced Semiconductor Engineering, Inc. | 2 | 0% |
| Micron Technology, Inc. | 1 | -50% |
| Intel Corporation | 0 | -100% |
| Samsung Electro-Mechanics Co., Ltd. | 0 | -100% |
| Renesas Electronics Corporation | 0 | — |
| Unimicron Technology Corporation | 0 | — |
Where to take this analysis
The figures on this page give the shape of the field. Turning that into a filing or licensing decision means drilling into specific claim language and specific assignee portfolios.
Run a claim-level comparison
Compare the SMD/NSMD pad-definition claims held by the leading assignees against your own substrate design to check for zone-based or geometry-specific overlaps before filing.
Open claim comparison in EurekaTrack the under-claimed branches
Monitor filing activity in coating/surface deposition and photoimageable dielectric classes, where record share is thin relative to the H01L/H05K core, for early signs of new entrants.
Set up a monitoring alert in EurekaFrequently asked questions
SMD pads have the solder mask opening smaller than the metal pad, so the mask itself defines the exposed pad area; NSMD pads have the opening larger than the pad, so the copper edge is exposed and the mask plays no role in defining the pad boundary. The distinction matters for patent claims because a large share of the filings in this dataset, including highly cited records like US8232641B2, claim specific combinations or zone-based mixes of the two structures rather than either structure in isolation. Reviewing claim language for whether a patent covers SMD, NSMD, or a defined mix across substrate zones is the first filter for freedom-to-operate work in this area.
Filing is concentrated at the top: the leading assignee in this dataset holds 485 of the 4,149 records in scope, and the top five assignees combined account for 38.5% of all records, rising to 51.4% for the top ten. Beyond that group there is a long tail of smaller filers, so most freedom-to-operate and licensing due diligence should start with the ranked leaders before extending to the wider field. Recent-year momentum also varies sharply within that leading group, with some large filers showing year-over-year declines in latest-year filings even as their cumulative portfolios remain the largest in the field.
Filings rose from 153 in 2017 to a peak of 372 in 2023, then declined from 284 in 2021 to 229 in 2024, a 19% drop over that three-year window. Figures for 2025 and 2026 are still incomplete in any patent dataset because publication typically lags actual filing by around 18 months, so the apparent tail-off in the most recent years should not be read as a real slowdown yet. The more reliable read is the 2021-to-2024 comparison, which shows the field cooling modestly from its 2023 peak rather than accelerating further.
Black pad defect is a known failure mode in electroless nickel immersion gold (ENIG) surface finishes, where excessive nickel corrosion during the immersion gold step weakens the solder joint. It is one of the specific technical triggers named in this dataset's search scope alongside solder mask defined structures and thermal cycling cracks, and it shows up in claims that tie a particular deposition sequence or composition to defect suppression. Because the coating and surface deposition class (C23C) carries a comparatively small 1.7% share of the 4,149 records, black-pad-specific claims are less crowded than the broader SMD/NSMD pad-geometry space and are worth checking separately in any prior-art search.
The core coverage sits in H01L (semiconductor devices, 63.9% of the 4,149 records) and H05K (printed circuits and assemblies, 43.0%), which together capture most solder mask, solder resist and surface-finish claims on packaging substrates. Secondary classes worth including are G03F for photoimageable dielectric and photolithography work (3.6%), C23C for coating and surface deposition (1.7%), and H01Q where antenna-in-package designs intersect with substrate finish (2.0%). Because a single record can carry several of these classes at once, searching only the largest class will miss filings that are classified primarily under a smaller, more specific code.
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Disclaimer. This page is generated from Patsnap Eureka data drawn from a limited snapshot of global patent and scientific-literature records, and is provided for general information and reference only.
Patent data carries inherent limitations: recent filings (typically the most recent 18–24 months) are under-counted due to standard publication lag; counts may be reported at either a patent-family or a patent-record basis and are not always directly comparable; classification, applicant-name, and citation data may contain errors, duplicates, or omissions; and the underlying search query defines and constrains the scope shown. As a result, the analysis may be incomplete or inaccurate and may not reflect the full technology landscape.
Nothing on this page constitutes an exhaustive prior-art, novelty, freedom-to-operate, or validity search, nor does it constitute legal, financial, investment, or professional advice, and it should not be relied upon as such. Any patent, commercial, or strategic decision should be verified independently and reviewed with qualified patent, legal, and domain professionals. Patsnap makes no warranties, express or implied, as to the accuracy, completeness, or fitness for any particular purpose of the information presented.
Machine translation. Assignee and organisation names originally recorded in Chinese, Japanese or Korean have been rendered into English by an AI translation step so that the tables stay readable. These renderings are best-effort and may not match a company’s registered English name; the original name is what the underlying patent record carries, and it is what any Eureka query launched from this page uses.