Through-Silicon Via Patents: Top Companies & Filing Trends 2026
- 32.8% sits with five companies. The top five assignees combine for 290 of 884 records in scope, a concentration that narrows where new filers can safely stake claims.
- Filings cooled after a 2022 peak. Activity hit 58 records in 2022 and growth ran -21% from 2021 (38) to 2024 (30) — the last year with a complete count.
- H01L dominates, but reveal-specific classes trail far behind. 91.1% of records touch H01L, while electroplating (C25D, 3.6%) and polishing chemistry (C09G, 2.3%) remain comparatively open.
Filing growth compares 2021 (38 records) with 2024 (30) — a three-year span. 2024 is the most recent year we treat as complete: publication lags filing by roughly 18 months, so 2025 onwards are still filling in and any growth rate that ends there would understate the field. Top-5 share is the combined record count of the five largest assignees divided by all 884 records in scope (CR5), not by the ranked leaders only.
What this landscape covers
Through-silicon via (TSV) formation and reveal spans the sequence of steps that turn a blind via etched into silicon into a working vertical interconnect: barrier and seed deposition, copper fill, and the reveal step — grinding, etching or polishing the wafer backside until the via is exposed without excessive copper protrusion. The search scope here combines core TSV terminology with claim-language anchors like via etch profile, keep out zone and reveal grinding, which pulls in the process-integration and packaging-level filings rather than generic 3D-IC prose.
884 published records fall inside this scope between 2015 and the 2026-07-31 cut-off. Because publication trails filing by roughly 18 months, the last one to two years of the trend will keep filling in after this snapshot and should not be read as a decline.
Filing trend and technology composition
Two views of the same 884 records: how filings moved year over year, and which IPC subclasses carry the claim density.
A 2022 peak followed by a cooling three-year span
Filings rose from 32 in 2017 to a peak of 58 in 2022, then eased to 30 by 2024 — a -21% move from 2021's 38, the most recent span that can be read as a complete trend given publication lag.
H01L carries the field; reveal-specific chemistry is thinner
H01L (semiconductor devices) appears on 91.1% of the 884 records, with H10W (22.5%) and H10P (16.0%) as secondary structural classes. Process-specific classes — C25D electroplating (3.6%), C09G polishing compositions (2.3%) and C23C coating (1.8%) — cover far fewer records, which is where reveal-step chemistry claims sit.
Shares are the percentage of the 884 records in scope. A patent can carry several IPC classes, so the shares add up to more than 100%.
Go deeper on Through-Silicon Via Formation and Reveal with Eureka
This page is one run against one query. Ask Eureka your own question about through-silicon via formation and reveal and every answer comes back with the patent numbers behind it.
Try EurekaThe most-cited prior art in this scope
US10199315B2 — Post zero via layer keep out zone over through silicon via reducing BEOL pumping effects
An IC structure and related method are provided. The IC structure includes a semiconductor substrate and a TSV disposed within it. A first interconnect layer includes V0 vias positioned laterally within the upper surface area of the TSV, while at least one second interconnect layer places its vias outside a keep-out zone positioned over the TSV. The method covers forming the first interconnect layer with V0 vias laterally within the TSV's upper surface area.Filed by GlobalFoundries U.S. Inc., published 2019-02-05.
| # | Publication no. | Patent title | Citations |
|---|---|---|---|
| 1 | US9048233B2 | Package systems having interposers | 1,068 |
| 2 | US20110291288A1 | Package systems having interposers | 685 |
| 3 | US7317256B2 | Electronic packaging including die with through silicon via | 444 |
| 4 | US20100193964A1 | Method of making 3D integrated circuits and structures formed thereby | 355 |
| 5 | US20090032951A1 | Small Area, Robust Silicon Via Structure and Process | 325 |
| 6 | US20150021785A1 | Hybrid bonding with through substrate via (TSV) | 291 |
| 7 | US8158515B2 | Method of making 3D integrated circuits | 282 |
| 8 | US20120025388A1 | Three-dimensional integrated circuit structure having improved power and thermal management | 272 |
| 9 | US8153520B1 | Thinning tungsten layer after through silicon via filling | 222 |
| 10 | US20100297844A1 | Integrated circuit system with through silicon via and method of manufacture thereof | 217 |
Citation counts inside this corpus favour older filings and signal influence on later drafting, not current commercial weight.
Each row carries its publication number; clicking a row searches Eureka by that number.
Put your own technology through the same analysis
Eureka on the web
When you want the answer in the next five minutes.
The agent works the prompt against patents and technical literature, citing every source.
Run your analysis now →MCP server & REST API
When it has to run inside your own pipeline.
Patent search, landscape analysis and assignee resolution as MCP tools. Drop them into any agent framework, or call REST directly.
Browse MCP servers →What the data means for filing strategy
Three patterns worth acting on before drafting claims in this space.
The top of the field is crowded, not the whole field
Five companies combine for 290 of the 884 records in scope. That concentration sits mostly in core via-etch and barrier/seed claims tied to H01L — new entrants competing head-on there face dense prior art from established fabs and memory makers.
Growth cooled after the 2022 peak, but the field isn't shrinking to zero
Filings peaked at 58 in 2022 before settling to 30 by 2024, the last year with a complete count. Several leading assignees show 0 filings in the latest tracked year, which is consistent with the ~18-month publication lag rather than an exit from the space.
Reveal chemistry is thinly claimed relative to structure
Structural classes H01L, H10W and H10P dominate the record set, but electroplating (C25D) and polishing compositions (C09G) each cover a small fraction of records. That gap is where reveal-step process chemistry — seed repair, protrusion control, slurry formulation — remains comparatively open.
Eureka can read the same corpus for gaps instead of for coverage: under-claimed branches adjacent to through-silicon via formation and reveal, with the prior art for and against each one.
Who is filing, and who has slowed
The ranked leaders span logic foundries, memory makers and IDMs, but recent-year momentum tells a different story from the cumulative count.
One filer well ahead of the field
The leading assignee holds 111 records, well clear of fifth place at 34 and tenth place at 22 — a steep drop-off that marks this as a field with one dominant filer and a long tail behind it.
Several leading assignees show zero latest-year filings
Multiple top-ranked assignees, including some of the largest cumulative filers, register zero records in the latest tracked year. Given the ~18-month publication lag, this reads as a reporting gap rather than a confirmed pullback — but it's worth re-checking against fresh publications before drawing conclusions.
Co-filing is limited and concentrated on one relationship
Only 10 co-assignee pairs appear in the dataset, and the strongest of them recur around a single organisation paired with different named inventors — suggesting most TSV reveal work is filed solo rather than through joint ventures.
| Assignee | Recent year | YoY |
|---|---|---|
| Taiwan Semiconductor Manufacturing Co., Ltd. (TSMC) | 0 | -100% |
| International Business Machines Corporation (IBM) | 0 | — |
| Samsung Electronics Co., Ltd. | 0 | -100% |
| SK Hynix Inc. | 0 | — |
| Nanya Technology Corporation | 0 | — |
| United Microelectronics Corporation (UMC) | 0 | — |
| ChangXin Memory Technologies, Inc. | 0 | — |
| Advanced Micro Devices, Inc. (AMD) | 0 | -100% |
Where to take this analysis
The dataset points to specific follow-up work depending on whether you're clearing a filing or scouting acquisition targets.
Screen the thinly-claimed process chemistry
Electroplating and polishing-composition classes cover a small share of the 884 records relative to the structural H01L core. Run a focused clearance search on reveal-step chemistry before assuming the space is occupied.
Explore white space in EurekaTrack the zero-filing signal through 2026 publications
Several top-10 assignees show zero latest-year filings, which may simply reflect publication lag. Re-run the momentum view once 2025-2026 data has filled in before treating any filer as inactive.
Set up monitoring in EurekaMap the leader's claim boundaries
With one assignee holding 111 of 884 records, understanding exactly which claim elements it controls — versus where its filings cluster procedurally — is the first step before drafting in adjacent territory.
Review leader filings in EurekaCommon questions on TSV formation and reveal patents
One assignee leads with 111 of the 884 records in this scope, well ahead of the fifth-ranked filer at 34 and the tenth at 22. The top five assignees combined hold 290 records, or 32.8% of the field, which is a meaningful concentration but still leaves more than two-thirds of filings spread across a long tail of other companies. The ranking covers 100 companies in total, drawn from logic foundries, memory makers and IDMs.
Filings rose to a peak of 58 records in 2022, then eased to 30 by 2024 — a -21% move from 2021's 38, which is the most recent span that can be treated as a complete trend. Years after 2024 will keep revising upward because publication typically lags filing by about 18 months, so the apparent drop in 2025-2026 counts should not yet be read as a slowdown. A clearer read on current momentum will only be possible once those later years finish publishing.
Reveal is the process of thinning the wafer backside — by grinding, etching or CMP — until the copper-filled via is exposed for bonding or redistribution routing, without leaving excessive copper protrusion or damaging the barrier and seed layers. It sits at the intersection of mechanical, chemical and electrical process control, which is why search scopes for this space pull in claim language like 'reveal grinding', 'copper protrusion' and 'keep out zone'. Because it's a late, integration-sensitive step, small process variations tend to attract narrow, defensible claims rather than broad structural ones.
Structural classes tied to H01L, H10W and H10P dominate the 884-record set, appearing on the large majority of filings, while process-chemistry classes like C25D (electroplating, 3.6%) and C09G (polishing compositions, 2.3%) cover a much smaller share. That gap points to reveal-step chemistry — seed-layer repair, protrusion-control formulations, and grinding-slurry composition — as comparatively open ground relative to the structural core. A freedom-to-operate search focused on those narrower classes is likely to surface less blocking prior art than a search centred on via structure itself.
US10199315B2, assigned to GlobalFoundries U.S. Inc. and published 2019-02-05, claims an IC structure where first-layer V0 vias sit directly on the TSV's upper surface while a second interconnect layer's vias are placed outside a defined keep-out zone over the TSV. The stated purpose is reducing BEOL pumping effects caused by TSV-induced stress during subsequent processing. Anyone designing via-last interconnect stacks with layered keep-out geometry over a TSV should check their layout rules against this claim scope specifically, rather than assuming general TSV prior art covers it.
Research Through-Silicon Via Formation and Reveal in depth with Eureka
Go past this page: query the whole through-silicon via formation and reveal corpus yourself, in your own scope.
Every answer comes back with patent numbers you can open.
Disclaimer. This page is generated from Patsnap Eureka data drawn from a limited snapshot of global patent and scientific-literature records, and is provided for general information and reference only.
Patent data carries inherent limitations: recent filings (typically the most recent 18–24 months) are under-counted due to standard publication lag; counts may be reported at either a patent-family or a patent-record basis and are not always directly comparable; classification, applicant-name, and citation data may contain errors, duplicates, or omissions; and the underlying search query defines and constrains the scope shown. As a result, the analysis may be incomplete or inaccurate and may not reflect the full technology landscape.
Nothing on this page constitutes an exhaustive prior-art, novelty, freedom-to-operate, or validity search, nor does it constitute legal, financial, investment, or professional advice, and it should not be relied upon as such. Any patent, commercial, or strategic decision should be verified independently and reviewed with qualified patent, legal, and domain professionals. Patsnap makes no warranties, express or implied, as to the accuracy, completeness, or fitness for any particular purpose of the information presented.
Machine translation. Assignee and organisation names originally recorded in Chinese, Japanese or Korean have been rendered into English by an AI translation step so that the tables stay readable. These renderings are best-effort and may not match a company’s registered English name; the original name is what the underlying patent record carries, and it is what any Eureka query launched from this page uses.