TMD Transistor Technology Landscape 2026 — PatSnap Eureka
TMD Transistor Technology Landscape 2026
Atomically thin MoS₂, WS₂, and WSe₂ channels are emerging as candidates to replace silicon at sub-7 nm nodes. This landscape maps 60+ patent and literature records across four core technical clusters from 2015 to 2026.
Beyond-Silicon Channels: The TMD Transistor Landscape
Transition metal dichalcogenide (TMD) transistors exploit layered MX₂ compounds — including MoS₂, WS₂, MoSe₂, and WSe₂ — that exhibit semiconducting behaviour in monolayer form. Key properties include direct bandgaps of 1–2 eV, high on/off current ratios, and natural body thicknesses below 1 nm, positioning TMDs as candidates for replacing silicon channels at advanced technology nodes.
Conventional FinFET and gate-all-around (GAA) architectures face fundamental scaling limits below 7 nm, creating demand for channel materials with superior electrostatic gate control and suppressed short-channel effects. TMD transistors offer both, and active patent families now span front-end-of-line (FEOL), back-end-of-line (BEOL), and monolithic 3D integration contexts.
The dataset covers four principal technical sub-domains: device architecture and contact engineering; thin-film deposition and crystal growth (CVD, CVT, MBE, electrostatic self-assembly); novel topologies including tunnel FETs and nanosheet GAA structures; and heterogeneous integration of TMD channels onto III-N, III-V, and silicon platforms.
In this dataset, Intel Corporation is the most prolific assignee with 14 distinct patent records, followed by TSMC and Samsung Electronics each with 7. Intel and TSMC together account for more than one-third of retrieved patent records in this dataset, reflecting heavy concentration among a small number of industrial players.
Filing Trends and Technical Cluster Distribution
Analysis of retrieved records reveals concentrated filing activity in contact engineering and stacked nanosheet architectures, with an acceleration in BEOL integration patents from 2024 to 2026.
Patent Records by Technical Cluster (Dataset Snapshot)
Contact engineering and stacked nanosheet GAA architectures together account for the largest share of retrieved records in this dataset, reflecting the two dominant industrial challenges of resistance reduction and device density scaling.
↗ Click bars to exploreTMD Patent Filing Activity by Period (Dataset Snapshot)
Filing activity in this dataset accelerated significantly from 2021 onwards, with 2024–2026 records reflecting the shift toward BEOL integration and manufacturability-focused inventions among the top assignees.
↗ Click bars to exploreKey TMD Transistor Application Domains Identified in Retrieved Records
Retrieved records span five distinct application domains, ranging from sub-7 nm CMOS logic scaling and BEOL integration to optoelectronics, III-N co-integration, and ultrafast optical switching.
Advanced Logic Sub-7 nm CMOS
The dominant application target in this dataset is CMOS logic scaling below 7 nm, with TMD channels proposed as FEOL or BEOL replacements for silicon. Intel’s TMD layer stack patents (2021–2026, US and EP) describe stoichiometric and sub-stoichiometric bilayer TMD channels optimised for transistor-level integration. Applied Materials’ February 2026 filings explicitly target low-temperature TMD growth compatible with back-end-of-line thermal budgets, critical for 3D chip stacking and chiplet architectures.
Logic ScalingOptoelectronics and Light-Emitting Devices
Yonsei University (UIF) filed a 2022 US patent demonstrating monolithic LED integration with TMD transistors without degrading LED characteristics. Review literature from 2017 and 2020 establishes TMDs as a platform for photodetectors, photovoltaics, and lasers. This application domain leverages the direct bandgap of monolayer TMDs, which is absent in bulk silicon and enables light emission at the transistor level.
OptoelectronicsIII-N / III-V Heterogeneous Co-Integration
Intel’s 2018 US patent describes techniques for co-integrating TMDC-based and III-N semiconductor transistors on a shared silicon substrate, enabling heterogeneous integration for mixed-signal and power applications. A related Intel patent (2020, US) covers TMD channels over III-nitride heteroepitaxial layers, filed originally in 2015 via PCT. This cluster targets RF and power-CMOS applications where GaN and TMD devices must share a common process flow.
Heterogeneous IntegrationLow-Power Tunnel FET Applications
TMD-based tunnel field-effect transistors (TFETs) are targeted at mobile and edge computing with sub-60 mV/dec switching requirements. IMEC’s 2020 US patent describes a TMD–III-V heterostructure TFET built by epitaxial growth, explicitly targeting sub-thermal switching. Simulation literature from 2015 and 2018 frames theoretical performance bounds for band-to-band tunneling in 2D TMD materials, establishing the foundation for this low-power application domain.
Low-Power LogicLeading Patent Assignees in TMD Transistors — Dataset Snapshot
In this dataset, Intel Corporation accounts for 14 of 60+ retrieved patent records, the highest single-assignee count in retrieved records, spanning stacked nanosheet, nanowire, SAM-directed growth, and selective metallization architectures across US and EP jurisdictions. TSMC and Samsung Electronics each hold 7 records in this dataset, focusing on FinFET channel formation and CVD thin-film deposition processes respectively.
Top Assignees by Patent Record Count in Retrieved Records (Dataset Snapshot)
↗ Click bars to exploreIntel Corporation
Intel holds 14 patent records in this dataset — the highest single-assignee count — with filing dates spanning 2018 to 2026 across US, EP, and WO jurisdictions. Key technology areas include stacked TMD nanosheet and nanowire GAA transistors (2022–2024), self-assembled monolayer directed TMD growth (2023), selective metallization for source/drain formation (2025), and TMD layer stack patents with active EP prosecution confirmed as of April 2026. Multiple Intel patents cover co-integration of TMD channels with III-N (GaN) devices on silicon substrates.
United StatesTaiwan Semiconductor Manufacturing Company
TSMC holds 7 patent records in this dataset with a filing date range from 2016 to 2022 across US jurisdiction. The foundational 2016 US patent describes TMD fin formation by direct deposition or conversion from non-TMD precursor with perpendicular or sloped fin sidewalls, and this family extended through continuations to 2022. A 2021 US patent targets TMD FET device formation for sub-10 nm technology node applications, confirming TSMC’s alignment of TMD channel technology with its advanced logic roadmap.
TaiwanForward-Looking Signals in TMD Transistor Patents (2024–2026)
The most recent filings in this dataset — clustered in 2024 to 2026 — reveal a shift from proof-of-concept to integration-readiness, with BEOL thermal budget compatibility, complementary n/p-type TMD logic, and phase-engineered in-situ contacts as leading technical frontiers.
BEOL TMD Integration: Applied Materials 2026 Filings
Applied Materials filed two BEOL/FEOL TMDC film formation patents in February 2026 — one via WO and one via US — explicitly targeting low-temperature TMD growth compatible with back-end-of-line thermal budgets. This is identified as critical for 3D chip stacking and chiplet integration architectures. Equipment suppliers filing on TMDC processes signals that process licensing opportunities may emerge for fabless design houses and system integrators monitoring this space.
Phase Engineering for In-Situ Contact Formation
Cambridge Enterprise’s 2025 WO patent on transition metal-based material phase engineering introduces a patterning method for layered TMDs enabling in-situ creation of conducting electrode regions from semiconducting TMD films — effectively eliminating the need for metal deposition. This converges with Stanford University’s 2017 gate-electrode-induced 2H-to-1T phase transformation patent. Together, these represent a manufacturing-relevant approach that may eliminate Schottky barriers entirely without separate metallization steps.
Intel vs. TSMC: TMD Transistor Patent Approaches Compared
Click any row to explore further.
| Dimension | Intel Corporation | Taiwan Semiconductor Manufacturing Company (TSMC) |
|---|---|---|
| Patent Record Count (this dataset) | 14 records (US, EP, WO) | 7 records (US) |
| Filing Date Range | 2018–2026 (active EP prosecution confirmed April 2026) | 2016–2022 |
| Primary Architecture | Stacked nanosheet / nanowire GAA; SAM-directed growth; selective metallization | TMD FinFET; fin formation by direct deposition or conversion from non-TMD precursor |
| Contact Engineering Approach | Monolayer TMD channel with multilayer doped TMD source/drain; selective metallization (2025 patent) | Elevated source/drain; fin sidewall geometry engineering |
| Integration Target | BEOL/FEOL, 3D IC, III-N co-integration (GaN on Si), chiplet architectures | Sub-10 nm logic node; FinFET-compatible CMOS flow |
| Jurisdictions | US, EP, WO (PCT) | US only (in this dataset) |
| Foundational Patent (earliest in dataset) | Co-integration of TMDC and III-N transistors (2018, US; originally filed 2015 PCT) | TMD FinFET channel formation by direct deposition or conversion (2016, US) |
| Unique Technology Focus | Self-assembled monolayer (SAM) directed TMD growth for batch channel deposition in nanoribbon stacks (2023) | Fin formation from TMD material converted from non-TMD precursor with perpendicular or sloped sidewalls |
Frequently Asked Questions: TMD Transistor Technology
TMD transistors exploit layered MX₂ compounds where M is a transition metal such as Mo, W, Re, or Ta, and X is a chalcogen such as S, Se, or Te. Specific materials referenced in this dataset include MoS₂, WS₂, MoSe₂, WSe₂, and MoTe₂. These exhibit semiconducting behaviour in monolayer form with direct bandgaps of 1–2 eV and natural body thicknesses below 1 nm.
TMD materials offer superior electrostatic gate control and suppressed short-channel effects compared to silicon, because their natural body thickness is below 1 nm. Conventional FinFET and gate-all-around (GAA) architectures face fundamental scaling limits below 7 nm, and TMD channels are proposed as drop-in or back-end-of-line replacements. Their high on/off current ratios further support logic scaling requirements.
Intel Corporation holds the most records in this dataset, with 14 distinct patent records across US, EP, and WO jurisdictions, covering architectures from stacked nanosheet and nanowire GAA transistors to selective metallization source/drain formation and III-N co-integration. TSMC and Samsung Electronics each hold 7 records in retrieved records.
The dominant device challenge identified in this dataset is Schottky barrier-induced contact resistance between semiconductor TMD channels and metal electrodes. Multiple assignees address this through metallic-phase TMD source/drain regions, chalcogen vacancy engineering, selective doping of multilayer TMD regions, and phase-engineered in-situ contacts. No single approach has achieved consensus in the dataset.
BEOL (back-end-of-line) compatible TMD transistors are fabricated using low-temperature processes that fit within the thermal budget constraints of back-end-of-line semiconductor manufacturing. Applied Materials filed two such patents in February 2026 explicitly targeting this compatibility. BEOL integration is critical for 3D chip stacking and chiplet integration architectures, and is identified in this dataset as an imminent strategic frontier.
Phase engineering refers to the conversion of TMD material between its semiconducting phase (typically 2H) and its metallic or semi-metallic phase (typically 1T or 1T’). Stanford University’s 2017 US patent describes gate-electrode-induced 2H-to-1T phase transformation, creating a reconfigurable semiconductor-to-metal switching mechanism. Cambridge Enterprise’s 2025 WO patent extends this to a patterning method enabling in-situ creation of conducting electrode regions from semiconducting TMD films, potentially eliminating Schottky barriers without separate metal deposition.
Data and insights on this page are based on a limited patent and literature dataset and are for reference only. Figures may not represent the complete technology landscape.