TSV Stress & Carrier Mobility in 3D Image Sensors — PatSnap Eureka
Reducing TSV Stress-Induced Carrier Mobility Degradation in 3D Stacked Image Sensors
Patent and literature evidence across 40+ documents reveals four dominant strategies — from tensile compensatory layers to cantilever stress relief structures — for protecting NMOS carrier mobility in thinned BSI pixel wafers bonded to logic dies.
How TSVs and Isolation Structures Degrade Carrier Mobility
The fundamental stress problem in 3D stacked image sensors originates from multiple co-located sources. Shallow trench isolation (STI) structures filled by high-density plasma (HDP) oxide generate significant compressive stress in the underlying silicon substrate and epitaxial layer. As documented by TSMC (2016), the STI formation process introduces damage and residual stress into the epitaxial layer, which can be mapped using Raman spectroscopy to quantify the local compressive state.
This compressive stress directly impacts NMOS transfer transistors adjacent to photodiodes, slowing electron transfer and reducing carrier mobility. TSVs introduce an additional, spatially concentrated stress field — their copper fill generates both radial compressive and axial tensile stress in the surrounding silicon. Yuecore Semiconductor (2025) explicitly identifies that TSV fabrication on the backside of CIS logic wafers causes stress concentration phenomena that threaten bonding interface integrity and device stability.
The stress is particularly harmful in thinned pixel wafers (3–5 µm thick BSI layers) bonded to logic substrates. Research from Hanyang University on 3D NAND flash memory (2021) showed that increasing compressive stress on polysilicon channels degrades bit-line current (Ion) through stress-induced electron mobility deterioration, and also causes negative threshold voltage shifts due to conduction band lowering — mechanisms directly transferable to transistor degradation adjacent to TSVs in stacked CIS arrays. Finite element analysis from National Cheng Kung University (2017) further validated a positive correlation between film stack stress and leakage current in CIS structures.
Beyond mechanical stress, TSVs in 3D stacked dies introduce substrate noise coupling as a secondary degradation mechanism. IMEC's study (2018) measured substrate noise maps in a 65 nm CMOS test vehicle, demonstrating that VDD and VSS TSVs excited through noise source circuitry generate overlapping noise waveforms whose amplitude distribution is governed by voltage division with the silicon substrate resistance — modulating threshold voltages and effective carrier mobility in adjacent transistors.
Four Proven Strategies for TSV Stress Mitigation
Patent evidence from TSMC, OmniVision, Yuecore Semiconductor, and academic institutions across five jurisdictions reveals a layered approach to protecting carrier mobility in 3D stacked CIS architectures.
Compensatory Tensile Stress Layer Deposition
TSMC's foundational approach deposits a stress layer with a controlled tensile second stress as part of the pre-metal dielectric (PMD) layer. This counteracts the compressive first stress induced by STI formation. When active pixel cell transistors are NMOS devices, the tensile stress layer simultaneously increases carrier mobility — turning a defect mitigation step into a performance enhancement. The workflow mandates Raman spectroscopy measurement of the substrate stress distribution prior to deposition, enabling site-specific tuning of the compensating film. Shanghai Huali Microelectronics extended this by depositing a tensile stress layer before the backside thinning step, followed by annealing and plasma or UV repair processes to maximize tensile stress magnitude.
TSMC (2011) · Shanghai Huali (2013)Cantilever-Beam Stress Relief Structures
Yuecore Semiconductor (2025) details fabrication of stress relief structures using a dual damascene process within the logic wafer, positioned in regions excluding TSV drilling locations and existing metal interconnects. The stress relief structure is a stacked beam (cantilever-beam) geometry formed by stacking horizontal and vertical metal elements. Key design parameters: relief structure width of 0.5–5 µm, length of 1–20 µm, and placement 3–10 µm from the nearest TSV. Adjacent TSVs must be spaced at least 7 µm apart. The structure can be formed as a single closed loop or multiple discontinuous segments around each TSV, absorbing and redistributing mechanical stress concentration before it propagates into the active pixel region.
Yuecore Semiconductor (2025)Doped Buffer Regions Between DTI and Photodiodes
TSMC's patents (2017, 2020) describe doped regions laterally positioned between backside deep trench isolation (BDTI) structures and image sensing elements. These regions prevent the image sensing element from interacting with interface defects near DTI structure edges — which are a primary source of both stress concentration and dark current generation — thereby simultaneously addressing mobility degradation and leakage current without altering the core transistor or TSV architecture. Research from the University of Electronic Science and Technology of China (2020) further demonstrated via numerical simulation that a trench-based structure placed around CoSi₂ and NiSi electrodes can reduce harmful tensile channel stress by approximately 50%, resulting in an approximately 7.5% increase in output current.
TSMC (2017, 2020) · ~50% stress reductionBSI Stress-Adjusting Films for Charge Collection
OmniVision Technologies (2013) discloses a stress adjusting layer deposited on the backside of the semiconductor layer. This layer establishes a stress characteristic that encourages photo-generated charge carriers to migrate toward the photosensitive region rather than recombining at the surface, reducing both dark current and mobility-related charge collection inefficiency. The corresponding Chinese patent (OmniVision, 2012) further clarifies that the backside surface stress can be tuned by forming stress loading layers to push photo-generated charge carriers away from defect-rich surface regions. This approach is particularly relevant for BSI sensors where the backside surface is the primary photon-collection interface.
OmniVision (2012, 2013)TSV Stress Mitigation: Data-Driven Insights
Quantitative analysis of patent activity and structural design parameters extracted from 40+ documents via PatSnap Eureka.
Innovation Timeline: TSV Stress Mitigation (2011–2025)
Patent filing activity shows three distinct waves: compensatory layers (2011–2015), architectural fault tolerance (2016–2020), and precision TSV relief structures (2021–2025).
TSV Cantilever Relief Structure Design Parameters
Key geometric constraints from Yuecore Semiconductor (2025) for dual damascene stress relief structures protecting TSV sites in CIS logic wafers.
Die Separation, TSV Elimination, and Fault Tolerance
When process-level mitigation is insufficient, architectural strategies physically decouple stress sources from the pixel active layer or provide system-level resilience against TSV-induced failures.
Thermal & Mechanical Isolation Layers Between Stacked Dies
Dehuai Semiconductor (2019) introduced a thermal insulation material layer between the logic wafer and the pixel wafer. While primarily designed to block heat-generated dark current, the thermal barrier also mechanically decouples the thin BSI pixel active layer (typically 3–5 µm) from stress-inducing logic-die processes, preventing thermomechanical stress transmission through the bonding interface.
Back-Electrode Direct Connection: Eliminating TSVs from the Pixel Array
Fudan University (2018) proposes replacing TSV-based vertical interconnects entirely with back-electrode connections directly linking the source region of photodetector MOSFETs to front-side signal-processing MOSFETs. This eliminates the need for high-aspect-ratio TSVs in the pixel array region, removing the principal stress source altogether while achieving pixel-parallel signal processing with each pixel having its own dedicated signal processor.
Who Is Leading TSV Stress Mitigation Innovation?
Taiwan Semiconductor Manufacturing Company (TSMC) is the most prolific and foundationally important assignee in this dataset, holding multiple active patents covering stress engineering methodology, Raman spectroscopy-guided process control, compensatory stress layer deposition, and doped region buffers for deep trench isolation. Their stress engineering patents span US, Korean, and Chinese jurisdictions and remain active, indicating sustained strategic investment in this area.
OmniVision Technologies holds active Chinese patents on BSI stress-adjusting films and multilayer pixel structures for crosstalk reduction, reflecting a parallel track focused on backside surface stress management. Their 2012 patent remains active and technically relevant to current BSI-TSV integration. Leading image sensor companies continue to build on these foundational approaches.
Yuecore Semiconductor represents the most recent innovation trend, with a 2025 pending patent specifically targeting TSV stress relief structure fabrication using dual damascene metal cantilever geometries — a highly specific and practical approach reflecting the maturation of TSV integration in commercial CIS products.
Tianjin University has developed a coherent family of patents addressing 3D stacked CIS readout fault tolerance for TSV failures, spanning cross-redundant, one-dimensional decode, and block-parallel architectural approaches. Samsung Electronics has entered the three-layer stacked CIS space with a 2024 architecture featuring through-electrodes with inverted trapezoidal cross-sections between chip layers, reducing misalignment and coupling noise. Access PatSnap's competitive landscape analytics to map the full assignee landscape across jurisdictions.
Innovation trends show a clear progression: early work (2011–2015) focused on compensatory stress layers and backside surface passivation; mid-period work (2016–2020) developed architectural TSV fault tolerance and thermal isolation between stacked dies; recent work (2021–2025) has moved toward precision TSV-specific stress relief structures, three-layer stacking with improved through-electrode geometries, and comprehensive charge management paths. The WIPO database confirms international filing activity across all five jurisdictions examined.
Seven Engineering Principles for TSV Stress Control
Synthesised from 40+ patent documents and academic literature, these principles form a decision framework for R&D teams designing 3D stacked CIS architectures.
Map Every TSV Stress Mitigation Patent Across 5 Jurisdictions
PatSnap Eureka searches US, CN, KR, JP, and WIPO filings simultaneously with AI-powered claim analysis.
TSV Stress & Carrier Mobility — Key Questions Answered
The fundamental stress problem originates from multiple co-located sources. Shallow trench isolation (STI) structures filled by high-density plasma (HDP) oxide generate significant compressive stress in the underlying silicon substrate and epitaxial layer. TSVs introduce an additional, spatially concentrated stress field — their copper fill generates both radial compressive and axial tensile stress in the surrounding silicon. This compressive stress directly impacts NMOS transfer transistors adjacent to photodiodes, slowing electron transfer and reducing carrier mobility.
Depositing a stress layer with a controlled tensile second stress as part of the pre-metal dielectric (PMD) layer counteracts the compressive first stress induced by STI formation. When the active pixel cell transistors are NMOS devices, a tensile stress layer simultaneously increases carrier mobility — turning a defect mitigation step into a performance enhancement. The workflow mandates Raman spectroscopy measurement of the substrate stress distribution prior to stress layer deposition, enabling site-specific tuning of the compensating film.
Stacked-beam (cantilever-beam) geometry stress relief structures are fabricated using a dual damascene process within the logic wafer, positioned in regions excluding the TSV drilling locations and existing metal interconnects. Key design parameters include: relief structure width of 0.5–5 µm, length of 1–20 µm, and placement 3–10 µm from the nearest TSV. Adjacent TSVs must be spaced at least 7 µm apart. The structure can be formed as a single closed loop or as multiple discontinuous segments around each TSV, effectively absorbing and redistributing the mechanical stress concentration before it can propagate into the active pixel region.
Doped regions laterally positioned between backside deep trench isolation (BDTI) structures and image sensing elements prevent the image sensing element from interacting with interface defects near DTI structure edges — which are a primary source of both stress concentration and dark current generation — thereby simultaneously addressing mobility degradation and leakage current without altering the core transistor or TSV architecture.
Fudan University's back-electrode connection architecture proposes replacing TSV-based vertical interconnects entirely with back-electrode connections directly linking the source region of photodetector MOSFETs to front-side signal-processing MOSFETs, eliminating the need for high-aspect-ratio TSVs in the pixel array region and thereby removing the principal stress source altogether. This architecture achieves pixel-parallel signal processing while maintaining high spatial resolution, since each pixel has its own dedicated signal processor without sharing via TSV routing.
Cross-redundant readout with linear interpolation in the ISP can recover signals from failed µbump, ADC, or TSV paths. One-dimensional decode readout partitions the pixel array into sub-arrays, allowing the ISP to detect anomalies and apply linear interpolation for failed TSV paths. A 2×2 pixel block architecture minimizes interconnect density and disperses failure-induced image artifacts. These approaches, developed by Tianjin University, provide system-level resilience when physical stress mitigation is insufficient.
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References
- Methods of Stress Engineering to Reduce Dark Current of CMOS Image Sensors — Taiwan Semiconductor Manufacturing Company, Ltd., 2016
- Stress Engineering to Reduce Dark Current of CMOS Image Sensors — Taiwan Semiconductor Manufacturing Company, Ltd., 2011
- Stress Engineering to Reduce Dark Current of CMOS Image Sensors — Taiwan Semiconductor Manufacturing Company, Ltd., 2014
- 减小图像传感器电学互扰的方法 — Shanghai Huali Microelectronics Corporation, 2013
- 一种硅通孔及应力消除层的加工方法及电子设备 — Yuecore Semiconductor Technology Co., Ltd., 2025
- 有源像素单元及在基板上形成有源像素单元的方法 — Taiwan Integrated Circuit Manufacturing Co., Ltd., 2011
- 具有应力膜的背侧照明图像传感器 — OmniVision Technologies (美商豪威科技股份有限公司), 2012
- Backside Illuminated Image Sensor with Stressed Film — OmniVision Technologies, Inc., 2013
- Impact of Residual Stress on a Polysilicon Channel in Scaled 3D NAND Flash Memory — Department of Electronics Engineering, Hanyang University, 2021
- Finite Element Analysis of Film Stack Architecture for Complementary Metal-Oxide-Semiconductor Image Sensors — National Cheng Kung University, 2017
- A Study on Substrate Noise Coupling Among TSVs in 3D Chip Stack — IMEC, 2018
- 用于背侧深沟槽隔离的额外的掺杂区域 — Taiwan Integrated Circuit Manufacturing Co., Ltd., 2020
- 用于背侧深沟槽隔离的额外的掺杂区域 — Taiwan Integrated Circuit Manufacturing Co., Ltd., 2017
- Trench Based Structure to Modulate the Stress Induced by Silicide Metallized Electrodes in Semiconductor Device — University of Electronic Science and Technology of China, 2020
- 3D堆叠式CMOS图像传感器及其制备方法 — Dehuai Semiconductor Co., Ltd., 2019
- 基于背电极连接的CMOS图像传感器及其制备方法 — Fudan University, 2018
- 基于交叉容错读出的3D堆叠结构图像传感器读出方法 — Tianjin University, 2016
- 基于一维解码读出的3D堆叠结构图像传感器读出方法 — Tianjin University, 2016
- 基于分块并行容错结构的3D堆叠图像传感器 — Tianjin University, 2019
- 一种减小应力堆叠背照式影像传感器的晶圆级封装结构 — Huajin Semiconductor Packaging Advanced Technology R&D Center, 2015
- 三层堆叠式图像传感器及其制造方法 — Samsung Electronics Co., Ltd., 2024
- WIPO — World Intellectual Property Organization Patent Database
- IEEE — Institute of Electrical and Electronics Engineers
- NIST — National Institute of Standards and Technology (Raman Spectroscopy Reference)
All data and statistics on this page are sourced from the references above and from PatSnap's proprietary innovation intelligence platform.
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