UCIe Chiplet Interconnect Standard: 2026 Patent Landscape
UCIe Chiplet Interconnect: 2026 Technology Landscape
UCIe ratified in March 2022 now underpins AI accelerators, HPC SoCs, and data center packaging strategies. This dataset spans 60+ patent and literature records from 2021–2026, mapping the key innovators and technology clusters.
UCIe Defines the Die-to-Die Interconnect Stack for Heterogeneous Chiplet Integration
UCIe is an open industry standard defining a complete die-to-die interconnect stack — physical layer (PHY), D2D adapter, protocol layer, and software model — enabling heterogeneous chiplet integration within a single semiconductor package. The specification supports standard-package and advanced-package form factors including 2.5D silicon interposer, organic substrate, EMIB, and hybrid bonding.
The protocol layer carries PCIe, Compute Express Link (CXL), or streaming transactions across chiplet boundaries. Five core innovation dimensions are active in this dataset: PHY and electrical interface design, protocol and adapter layer, 3D/2.5D packaging integration, test and debug infrastructure, and application-layer integration for HBM memory and AI accelerators.
Filings span 2021 through mid-2026, with a strong concentration of active records in 2024–2026. Early foundations in 2020–2022 established conceptual bases for chiplet heterogeneous integration. Standards-driven build-out from 2022–2023 followed UCIe 1.0 publication in March 2022, triggering implementation filings from US, Chinese, and Taiwanese assignees.
The landscape in retrieved records is moderately concentrated at the top — Intel alone accounts for at least 16 distinct filings covering all four technology clusters — but the long tail is diversifying rapidly, with at least 7 distinct Chinese assignees, Korean startup Rebellions Inc., and fabless IP vendors including Eliyan, Synopsys, and Unifabrix all staking positions in this dataset.
Four Technology Clusters and Accelerating Filing Activity Shape the UCIe Patent Landscape
Analysis of retrieved records reveals four primary innovation clusters — PHY/electrical interface, protocol and link layer, 3D packaging integration, and test/debug infrastructure — with filing intensity concentrated in 2024–2026 as the field transitions from standard definition to product implementation.
UCIe Patent Records by Technology Cluster (Dataset Snapshot)
PHY and electrical interface design is the most heavily represented cluster in this dataset, followed by protocol/adapter layer and 3D packaging integration, reflecting the maturation of physical implementation work after UCIe 1.0 ratification.
↗ Click bars to exploreUCIe Patent Filing Activity by Year (Dataset Snapshot)
Filing activity in this dataset accelerated sharply from 2023 onward, with 2025 representing the peak year of records, confirming the field is in a rapid scale-up phase following UCIe 1.0 ratification in March 2022.
↗ Click bars to exploreUCIe Deployment Across AI Accelerators, Data Centers, Photonics, and Memory Fabric
Retrieved records reveal five distinct application verticals where UCIe is being implemented: AI accelerators and HPC, data center and cloud infrastructure, multi-protocol memory fabric and retimers, photonics and optical interconnect, and heterogeneous SoC systems.
AI Accelerators and HBM Integration
Multiple 2025–2026 filings from Intel, Shanghai QuXin (Hefei affiliate), and individual inventor Kolluru propose routing UCIe signals directly over organic package substrates or redistribution layers to connect SoC compute dies with HBM stack dies, bypassing CoWoS/silicon interposer constraints. Intel’s 2025 US patent covers on-package D2D memory interconnects supporting symmetric and asymmetric lane configurations based on workload. Shanghai QuXin’s 2025 TW filing specifically targets AI chip memory scaling by integrating SoC dies with HBM stack dies through UCIe interfaces without silicon interposers, addressing CoWoS capacity bottlenecks.
AI / HPCData Center and Cloud Infrastructure
Meta Platforms’ 2024 US/WO patent describes server-class CPU SoCs with integrated accelerator chiplets communicating over UCIe D2D interfaces, including CXL and AXI protocol tunneling across chiplet boundaries. Google’s 2024 US patent introduces a security-isolated IT services management chiplet connected to processing chiplets via a UCIe-compatible D2D interconnect with physical air-gap isolation, targeting cloud server manageability. Intel’s 2024 US patent addresses CXL-based processor chiplet access arbitration through interconnect switches, applicable to disaggregated memory architectures in data centers.
Data CenterPhotonics and Optical Interconnect
Lightmatter’s 2026 US pending patent is the first in this dataset to embed UCIe as an inter-tile electrical standard within a photonic computing platform. The multi-reticle device integrates UCIe-AP (Advanced Package) and UCIe-SP (Standard Package) variants as the electrical communication standard within electro-optical tiles containing HBM arrays and photonic interconnects. This filing signals UCIe’s expansion beyond traditional silicon packages into hybrid optical-electrical compute tiles for next-generation optical computing platforms.
PhotonicsMulti-Protocol Memory Fabric and Retimers
Unifabrix’s 2026 US active patent implements a drop-in PCIe retimer form-factor silicon chip supporting UCIe PHY as one of multiple physical interface options, enabling protocol translation between NVLink, CXL, and CHI domains within data center memory fabrics. Rebellions Inc.’s 2025 US active patent describes a multi-chiplet system using UCIe flit-based protocol mode supporting PCIe Non-Flit/Flit Mode, CXL 68B/256B Fleet Mode, and Streaming Protocol for heterogeneous protocol conversion between chiplets from different vendors. Together these filings signal UCIe moving from on-package to near-package and inter-package domains.
Memory FabricLeading Patent Assignees in UCIe Chiplet Interconnect — Dataset Snapshot
In retrieved records, Intel Corporation is the largest contributor with at least 16 distinct patent filings covering all four UCIe technology clusters across US, WO, DE, EP, and CN jurisdictions. Qualcomm Incorporated follows with 7+ records in this dataset, concentrated on link reliability, sideband mechanisms, and error recovery.
Top UCIe Assignees by Filing Count in Retrieved Records (Dataset Snapshot)
↗ Click bars to exploreIntel Corporation
Intel has at least 16 distinct patent records in this dataset spanning WO, US, DE, EP, and CN jurisdictions, with filings ranging from 2023 to 2026. Coverage spans all four UCIe technology clusters: PHY design (asymmetric data rates, on-package D2D memory interconnects), protocol layer (management transport packets, sideband-only UCIe links for SiP), 3D packaging (UCIe-3D as on-package interconnect), and test/debug (unified test and debug chiplet architecture, GPIO-based low-speed test paths). Key active patents include the 2025 US on-package D2D interconnect for memory using UCIe PHY and the 2026 US unified test and debug chiplet architecture.
United StatesQualcomm Incorporated
Qualcomm has 7+ patent records in this dataset filed across US, WO, IN, TW, and CN jurisdictions, with filings concentrated in 2025–2026. Technology focus is on UCIe link reliability and protocol robustness: the 2025 US active patent introduces UCIe link reconfiguration for selective sideband switching after reset in multi-module chiplets, while a separate 2025 US pending patent covers partial UCIe link error recovery — isolating an errored mainband or sideband segment and re-training only that portion. A 2026 IN filing covers interconnects between chiplets and link initialization protocols.
United StatesSix Forward-Looking UCIe Directions Active in 2025–2026 Filings
Filings dated 2025–2026 in this dataset point to six active emerging directions: HBM integration without silicon interposers, UCIe 2.0 sideband-only and sub-specification variants, electro-optical integration, EDA-native UCIe routing tools, multi-protocol retimers, and chiplet-native security isolation.
UCIe for HBM Without Silicon Interposers
Multiple 2025–2026 filings from Intel, Shanghai QuXin, and individual inventor Kolluru propose routing UCIe signals directly over organic package substrates or redistribution layers to connect SoC compute dies with HBM stack dies, bypassing CoWoS/silicon interposer constraints. Intel’s 2025 US patent on on-package memory with UCIe and Kolluru’s 2026 US filing on chiplet interconnect for HBM devices both eliminate EMIB/interposer requirements. This direction is a direct response to CoWoS supply bottlenecks in AI chip production, with at least 5 independent assignees in this dataset pursuing this approach.
EDA-Native UCIe Routing and Sub-Specification Variants
Synopsys’ 2026 US active patent on interposer routing for UCIe channels by partitioning into subchannels is the first EDA-tool-focused UCIe patent in this dataset, enabling automated UCIe-compliant place-and-route through passive silicon interposers. Intel’s 2025 US patent on sideband-only UCIe links explicitly references UCIe 2.0 feature sets, while Lightmatter’s 2026 filing references UCIe-AP (Advanced Package) and UCIe-SP (Standard Package) variants separately. These filings indicate active ecosystem divergence into sub-specifications targeting distinct packaging tiers and commercialization of UCIe-aware routing tooling.
UCIe Physical Layer vs. Protocol Layer: Innovation Focus Comparison
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| Dimension | PHY & Electrical Interface Cluster | Protocol & Adapter Layer Cluster |
|---|---|---|
| Physical Layer (PHY) | Signal integrity, clocking, bump map layout, asymmetric data rates, interposer routing | Flit formats, sideband reliability, management transport, link training state machine (LTSSM) |
| Leading Assignees in Dataset | Intel, Shanghai Biren Technology, Synopsys, MediaTek | Qualcomm, Intel, Gechuang Communications, Rebellions Inc. |
| Representative Filing | Intel 2025 US: On-Package D2D Interconnect for Memory Using UCIe PHY (active) | Qualcomm 2025 US: Mechanism to Improve the Reliability of Sideband in Chiplets (active) |
| Packaging Integration | Standard package, advanced package (2.5D, 3D), interposer, organic substrate, hybrid bonding | System-in-Package (SiP), multi-module chiplets, daisy-chain topologies |
| Primary Challenge Addressed | Density, signal integrity, asymmetric bandwidth, interposer routing automation | Sideband reliability in multi-module configurations, error recovery without full link reset |
| Filing Jurisdictions | US, CN, TW (dominant); DE, EP (Intel-specific) | US, WO, IN, TW, CN (Qualcomm multi-jurisdictional); CN (Gechuang) |
| Records in Dataset Snapshot | ~15 records in this dataset | ~12 records in this dataset |
Frequently Asked Questions: UCIe Chiplet Interconnect Patents
UCIe (Universal Chiplet Interconnect Express) is an open industry standard defining a complete die-to-die interconnect stack — physical layer (PHY), D2D adapter, protocol layer, and software model — enabling heterogeneous chiplet integration within a single semiconductor package. UCIe 1.0 was ratified in March 2022, triggering a wave of implementation filings.
In this dataset, Intel Corporation is the largest contributor with at least 16 distinct patent records spanning WO, US, DE, EP, and CN jurisdictions. Intel covers all four technology clusters: PHY, protocol, 3D packaging, and test/debug.
The four primary innovation clusters in retrieved records are: (1) PHY and electrical interface design covering bump map layout, signal integrity, and asymmetric data rates; (2) protocol and adapter layer covering flit formats, sideband reliability, and error recovery; (3) 3D/2.5D packaging integration covering UCIe-3D, interposer routing, hybrid bonding, and USR chiplets; and (4) test, debug, and validation infrastructure.
Yes. At least 7 distinct Chinese assignees appear in this dataset filing UCIe-related patents, including Shanghai Biren Technology Co., Ltd. with 5+ CN records on I/O layout and test methods, Shanghai QuXin Integrated Circuit Design with 4+ records focused on HBM-UCIe semiconductor devices, and Gechuang Communications with a 2026 CN protocol layer data transmission circuit patent.
Multiple 2025–2026 filings from Intel, Shanghai QuXin, and inventor Kolluru propose routing UCIe signals directly over organic package substrates or redistribution layers to connect SoC compute dies with HBM stack dies without silicon interposers. This approach directly addresses CoWoS supply bottlenecks in AI chip production and is actively pursued by at least 5 independent assignees in this dataset.
Six forward-looking directions are active in 2025–2026 filings in this dataset: UCIe for HBM integration without silicon interposers; UCIe 2.0 sideband-only links and UCIe-AP/SP sub-specification variants; UCIe embedded in electro-optical photonic computing tiles (Lightmatter 2026); EDA-automated UCIe interposer routing tools (Synopsys 2026); multi-protocol retimers with UCIe PHY (Unifabrix 2026); and chiplet-native security and management isolation (Google 2024–2025).
Data and insights on this page are based on a limited patent and literature dataset and are for reference only. Figures may not represent the complete technology landscape.