UCIe Die-to-Die Chiplet Integration — PatSnap Eureka
UCIe Die-to-Die Interface: Heterogeneous Chiplet Integration Across Foundries
The Universal Chiplet Interconnect Express standard defines an open three-layer stack — PHY, D2D Adapter, and Protocol Layer — that decouples die sourcing from foundry process, enabling cross-foundry heterogeneous integration at scale. Over 35 patent filings from Intel, Qualcomm, and Shanghai Biren Technology map the innovation landscape.
How UCIe's Three-Layer Stack Enables Cross-Foundry Interoperability
UCIe achieves foundry-agnostic interoperability through a rigidly defined three-layer stack: a Physical Layer (PHY), a Die-to-Die Adapter (D2D Adapter), and a Protocol Layer. The PHY manages the actual electrical signal transmission over microbump or hybrid-bond interconnects; the adapter handles flow control, flit formatting, and ordering; and the protocol layer translates on-chip network transactions into UCIe-standard transaction packets.
As described in Intel Corporation's 2024 filing, "UCIe provides high-bandwidth, low-latency, high power efficiency and high cost-effective on-package connectivity between chiplets" and explicitly enables "interconnection of different devices from different vendors and different factories at different technology nodes." The standard D2D adapter interfaces are formalized through two defined logical interfaces: the FDI (Flit-aware Die-to-Die Interface) between the protocol layer and the adapter, and the RDI (Raw Die-to-Die Interface) between the adapter and the PHY.
This architecture supports multiple overlay protocols — CXL flit mode, PCIe flit mode, and a raw/streaming mode — enabling customers to reuse the same physical link for diverse traffic types across multiple protocol generations. Capability negotiation at link bring-up is formalized via a parameter exchange mechanism: a D2D adapter reads capabilities from registers, transmits a first capabilities advertisement message to the link partner, receives a second capabilities advertisement message in return, and resolves a final link configuration. Learn more about PatSnap's patent landscape analytics for semiconductor interconnect research.
The sideband interface is a critical enabler of cross-foundry bring-up. Intel's sideband filing details a PHY that includes redundant sideband data and clock receivers — a first and second sideband pair — from which a working sideband is selected at initialization. Critically, the sideband supports die rotation and die mirroring so that the same die can be instantiated in multiple physical orientations on a package without requiring a dedicated bonding orientation mask layer. Standards bodies such as JEDEC and IEEE provide complementary interface specifications that UCIe builds upon.
UCIe Innovation Landscape: Who's Filing and What They're Protecting
Analysis of 35+ patent records across US, CN, WO, DE, TW, IN, and JP jurisdictions reveals concentrated innovation across four technical clusters, led by Intel, Qualcomm, and Shanghai Biren Technology.
UCIe Patent Records by Leading Assignee
Intel leads with at least 9 records establishing the normative UCIe specification; Qualcomm follows with 8 records focused on link reliability; Shanghai Biren Technology contributes 7 records on I/O layout and debug infrastructure.
UCIe Innovation by Technical Cluster
Four dominant technical themes emerge from the dataset: PHY/Adapter/Protocol stack architecture, memory interface extensions (LPDDR/HBM), link reliability and training, and I/O layout with debug infrastructure.
Extending UCIe to LPDDR, HBM, and 3D-DRAM as a Unified On-Package Fabric
A pivotal application of cross-foundry UCIe is bridging the traditionally proprietary memory interface gap — replacing LPDDR and HBM-specific physical interfaces with a unified UCIe adapter layer.
UCIe PHY as Unified Memory Fabric for LPDDR
Intel's filing describes an architecture where "UCIe interface logic implements a mapping between the UCIe interface and the memory interface," translating LPDDR command/address/data signals into UCIe flits. The described solution is positioned as a unified solution spanning client (handheld, notebook) and server/HPC segments, using the same on-package LPDDR memory die across SoC variants differentiated only by their UCIe adapter configuration.
Unified client + server LPDDR solutionAsymmetric Data Rates for Memory Bandwidth Optimization
Asymmetric data rate support is particularly important for memory applications, where read and write bandwidth profiles differ. Intel's US and German filings disclose techniques allowing the UCIe PHY to operate at different data rates in the transmit and receive directions, reducing power and silicon area for memory interfaces where bandwidth is inherently directional.
Asymmetric TX/RX data ratesHBM Integration via UCIe Without Silicon Interposer
A SoC die carries first UCIe interface IP at its edge, while a storage module comprises a joint die containing HBM IP and second UCIe interface IP interconnected via an on-chip bus. Critically, "the second interconnection structure does not include a silicon interposer," achieving direct UCIe-based die-to-die connectivity between the SoC and the HBM storage module without a costly silicon bridge, improving yield and reducing thermal interference. See PatSnap's materials and advanced packaging solutions for related research.
No silicon interposer requiredMulti-UCIe-Interface 3D-DRAM Bridge Chip for Scale-Out Memory
A bridge chip die includes one or more UCIe interfaces, multiple DRAM controllers, a cache controller, and SRAM. Multiple UCIe interfaces allow the same DRAM storage module to be simultaneously accessed by multiple external SoC dies, enabling modular scale-out memory architectures across heterogeneous chiplet pools. The JEDEC HBM specification provides the underlying memory standard that UCIe bridges into the chiplet ecosystem.
Simultaneous multi-SoC DRAM accessQualcomm's Multi-Jurisdictional Portfolio: Training, Sideband, and Error Recovery
Because UCIe links may connect dies fabricated at different nodes with different process corners, robust link training and in-field reliability mechanisms are essential. Qualcomm leads this cluster with comprehensive cross-jurisdictional coverage.
Partial-Link Error Recovery Without Full Retraining
Qualcomm's multi-jurisdictional filing (US, TW, WO, IN) identifies the first part of the UCIe link where an error has occurred and retrains only that portion, while maintaining the second, error-free part of the link active and available for data transmission. This is critical in heterogeneous integration scenarios where individual lane defects should not disrupt the entire link.
Multi-Module Sideband Reliability for Complex Chiplets
Qualcomm's invention handles the scenario where a multi-module chiplet has multiple functional sidebands — because a single physical chiplet package contains multiple independent logic modules each requiring their own UCIe sideband — by reading sideband data that identifies the functional sideband to initialize following a reset state, and then selectively initializing the correct sideband.
UCIe Innovator Rankings: Filing Depth and Technical Focus
Based on filing frequency and technical depth in the 35+ record dataset, the primary innovators can be ranked and characterized across jurisdiction reach and innovation theme.
| Company | Records | Primary Innovation Theme | Key Jurisdictions | Strategic Focus |
|---|---|---|---|---|
| Intel Corporation | ≥9 LEAD | PHY/Adapter/Protocol stack, memory integration, 3D UCIe | US, WO, DE, CN, JP | Normative spec stewardship and foundational IP |
| Qualcomm Incorporated | ≥8 | Link reliability, training optimization, sideband management | US, TW, WO, IN | Mobile and edge: power-efficient link training and recovery |
| Shanghai Biren Technology | ≥7 | I/O layout, design verification, performance monitoring, debug | CN | AI accelerator chipsets with high-density I/O and post-silicon tooling |
| Hefei Kuixin IC Design | ≥2 | HBM-plus-UCIe storage module architecture | TW | AI chip memory bandwidth scaling without silicon interposers |
Track every UCIe filer across all jurisdictions
PatSnap Eureka maps assignee portfolios, filing velocity, and claim overlap in real time.
Shanghai Biren Technology: Solving High-Density UCIe I/O and Post-Silicon Bring-Up
The high lane count demanded by UCIe's bandwidth targets drives specific innovations in I/O layout and on-chip verification. Since UCIe I/O interfaces must scale to hundreds or thousands of pins per die edge, traditional one-dimensional I/O placement is insufficient. Shanghai Biren Technology's 2025 filing addresses the challenge that "the number of UCIe I/O interfaces is extremely large" and that one-dimensional layouts "can no longer meet design requirements."
The invention proposes a two-dimensional matrix layout where each UCIe I/O interface group contains two parallel I/O interface queues with a reference level generation module placed between them. The reference level output trace runs parallel to both queues between them, and the reference level input traces of each I/O module in both queues are coupled directly to this central trace. This symmetric co-placement minimizes reference level routing length, improves reference voltage stability, and reduces power-on training time.
Debug and diagnostics infrastructure during and after silicon bring-up is covered in a complementary Biren filing that introduces pause state registers and bypass registers that can halt a chiplet's LTSSM state machine at any transition point, inject correction signals, and then resume. This controllable state-machine interruption mechanism enables post-silicon debug without requiring full link reinitialization — critical for diagnosing training failures in heterogeneous assemblies where root cause attribution to a specific die or foundry process corner is non-trivial.
A further Biren filing stores debug chains including timestamp register information and error transmission information via a DMA module to system bus memory, enabling time-ordered, dynamic-length debug records that persist across link resets. For enterprise IP teams managing multi-foundry chiplet programs, PatSnap's trust center details how IP data is secured. The Semiconductor Digest provides additional industry context on advanced packaging debug challenges.
UCIe Patent Filing Geography: Global Standardization Momentum
The dataset covers jurisdictions spanning the US, China, Germany, Taiwan, India, Japan, and PCT/WO filings, reflecting the global standardization momentum behind UCIe as an open die-to-die interconnect standard.
UCIe Filing Jurisdictions in This Dataset
Seven distinct patent jurisdictions covered, with US and CN leading by volume, reflecting both Intel's US-centric core IP and Chinese industry adoption led by Shanghai Biren Technology and Hefei Kuixin.
UCIe Architecture Extension: From 2D to 3D Stacking
Intel's UCIe-3D filing extends the standardized bring-up and protocol stack into vertical die stacking via face-to-face or face-to-back bonded configurations, coupling chiplets' physical layer modules through Network-on-Chip (NoC) controller logic.
UCIe Die-to-Die Interface — key questions answered
UCIe achieves foundry-agnostic interoperability through a rigidly defined three-layer stack: a Physical Layer (PHY), a Die-to-Die Adapter (D2D Adapter), and a Protocol Layer. This separation of concerns means that a chiplet fabricated at TSMC can interoperate on the same package with a die fabricated at Intel Foundry, as long as both implement compliant PHY and adapter interfaces.
The standard D2D adapter interfaces are formalized through two defined logical interfaces: the FDI (Flit-aware Die-to-Die Interface) between the protocol layer and the adapter, and the RDI (Raw Die-to-Die Interface) between the adapter and the PHY. This architecture supports multiple overlay protocols — CXL flit mode, PCIe flit mode, and a raw/streaming mode — enabling customers to reuse the same physical link for diverse traffic types across multiple protocol generations.
HBM integration via UCIe is directly targeted in a filing from Hefei Kuixin IC Design, which describes an architecture where a SoC die carries first UCIe interface IP at its edge, while a storage module comprises a joint die containing HBM IP and second UCIe interface IP interconnected via an on-chip bus. The joint die then connects to an HBM stack die via a first interconnection structure. Critically, the second interconnection structure does not include a silicon interposer, achieving direct UCIe-based die-to-die connectivity between the SoC and the HBM storage module without a costly silicon bridge, improving yield and reducing thermal interference.
Qualcomm's invention identifies the first part of the UCIe link where an error has occurred and retrains only that portion, while maintaining the second, error-free part of the link active and available for data transmission. This partial-link recovery approach is critical in heterogeneous integration scenarios where individual lane defects (which are more likely when combining dies from different foundries with potentially different bump pitch and alignment tolerances) should not disrupt the entire link.
A D2D adapter reads a set of capabilities from registers and transmits a first capabilities advertisement message to the link partner adapter, receives a second capabilities advertisement message in return, and then resolves a final link configuration. This negotiated bring-up is essential when dies from different foundries may support different optional UCIe features (e.g., asymmetric data rates, lane repair counts), allowing a graceful intersection of capabilities rather than a hard dependency on identical silicon.
The dominant assignees by filing frequency are Intel Corporation (appearing in at least 9 records), Qualcomm Incorporated (at least 8 records), and Shanghai Biren Technology (at least 7 records), followed by contributors from Chinese academia and smaller semiconductor houses including Nanjing University of Information Science and Technology, Hefei Kuixin IC Design, and ZTE Microelectronics. The dataset covers jurisdictions spanning the US, China, Germany, Taiwan, India, Japan, and PCT/WO filings.
Still have questions? Let PatSnap Eureka answer them for you.
Ask Eureka About UCIe PatentsAccelerate Your UCIe and Chiplet Integration R&D with AI Patent Intelligence
Join 18,000+ innovators already using PatSnap Eureka to accelerate their R&D. Search 35+ UCIe filings, map assignee portfolios, and identify white spaces across all jurisdictions in minutes.
References
- Die-to-Die Interconnect — Intel Corporation, 2024
- Standard Interface for Die-to-Die (D2D) Interconnect Stack — Intel Corporation, 2024
- Sideband Interface for Die-to-Die Interconnect — Intel Corporation, 2024
- Parameter Exchange for a Die-to-Die Interconnect — Intel Corporation, 2023 (WO)
- On-Package Die-to-Die (D2D) Interconnect for Memory Using UCIe PHY — Intel Corporation, 2024 (US)
- Asymmetrical Data Rates for High Speed Interconnects — Intel Corporation, 2024 (US)
- Asymmetric Data Rates for High-Speed Interconnections — Intel Corporation, 2025 (DE)
- Three Dimensional Universal Chiplet Interconnect as On-Package Interconnect — Intel Corporation, 2024 (US)
- Semiconductor Device Based on UCIe Interface — Hefei Kuixin IC Design, 2025 (TW)
- Chiplet Interconnect for High Bandwidth Memory Devices — Independent Inventor, 2026 (US)
- 3D-DRAM-Based External Memory Solution — Shanghai Fushen Technology, 2025
- Performance and Power Efficient Link Error Recovery in Inter-chiplet Communication — Qualcomm Incorporated, 2025 (US)
- Mechanism to Improve the Reliability of Sideband in Chiplets — Qualcomm Incorporated, 2025 (US)
- Interconnects Between Chiplets and Related Link Initialization Protocols — Qualcomm Incorporated, 2025 (US)
- Mechanism to Enhance Link Bandwidth in Interconnects — Qualcomm Incorporated, 2025 (US)
- UCIe Input/Output Interface Layout Structure, Circuit, and Chip — Shanghai Biren Technology, 2025 (CN)
- UCIe Design Module Test Method, Device, Electronic Equipment, and Storage Medium — Shanghai Biren Technology, 2025 (CN)
- UCIe-Based Fault Diagnosis and Debug Method — Shanghai Biren Technology, 2025 (CN)
- UCIe-Based Debug Information Recording Method — Shanghai Biren Technology, 2025 (CN)
- UCIe Performance Information Acquisition Method, Chiplet, Chip, and Data Processing Device — Shanghai Biren Technology, 2025 (CN)
- JEDEC — HBM and LPDDR Memory Interface Standards
- IEEE — Semiconductor Packaging and Interconnect Standards
- Semiconductor Digest — Advanced Packaging Industry Coverage
All data and statistics on this page are sourced from the references above and from PatSnap's proprietary innovation intelligence platform.
PatSnap Eureka searches patents and research to answer instantly.