Underfill material is claimed for the narrow gap between a flip-chip die and its substrate, where it flows by capillary action or is pre-applied before bonding to reduce stress from thermal expansion mismatch. Epoxy molding compound is claimed as the bulk encapsulant that covers the whole package body, protecting it from moisture and mechanical damage. Both appear in this dataset's search string because they are formulated with overlapping filler and resin chemistry, and many assignees file across both, but the claims themselves target different physical locations in the package and different failure modes.

The dataset's assignee ranking shows activity concentrated among large integrated-device manufacturers and packaging specialists rather than a single dominant filer, with several major semiconductor companies among the top holders. Recent-year momentum for these leading assignees has flattened to zero new filings in the latest tracked year across the names checked, which is consistent with the overall peak-and-decline filing trend rather than indicating any one company has stopped competing. Reviewing the full ranked table alongside filing dates gives a clearer picture than any single company name in isolation.

The trend data shows filings peaked at 25 in 2022 after rising from 16 in 2017, then declined in subsequent years. Part of that apparent decline is a reporting artefact: publication lags filing by roughly 18 months, so the most recent year or two in any patent trend is always undercounted relative to where it will eventually settle. The remainder likely reflects a maturing claim landscape, since the most-cited foundational patents in this set date back to the 1990s and 2000s, meaning much of the core flip-chip underfill mechanism space was already claimed before the 2022 peak.

Filler loading refers to the weight percentage of solid particles, typically silica, mixed into the liquid resin before cure, and it is one of the most frequently claimed numeric parameters in this dataset because it directly controls the cured material's coefficient of thermal expansion. Higher filler loading generally lowers CTE and improves reliability under thermal cycling, but it also affects flow under the die during dispense and the achievable particle size distribution. Claims in this field often stack a filler-loading threshold together with particle size, CTE and glass transition temperature limits, as seen in the representative record from Intel, which makes single-variable design-arounds harder than they first appear.

The technology composition data shows H01L (core semiconductor device packaging) accounts for 503 of 536 records, while adhesive claims under C09J and printed-circuit-assembly claims under H05K each sit at under 30 records. That gap points to the interface between cured underfill or molding compound and board-level assembly, rather than the die-to-substrate gap itself, as comparatively under-claimed. Any new filing there still needs to clear the dense prior art around filler loading and CTE, but it can differentiate by tying those parameters to board-level reliability testing rather than die-level packaging alone.