Van der Waals Heterostructure Transistors 2026
Van der Waals Heterostructure Transistors
Atomically thin 2D material stacks assembled without lattice-matching constraints are enabling sub-10 nm channel devices with sub-Boltzmann subthreshold swings. This dataset snapshot covers core TFET, VFET, and reconfigurable transistor architectures from 2014 to 2026.
Post-CMOS Transistors Built from 2D Material Stacks
Van der Waals heterostructure transistors exploit weak interlayer forces between two-dimensional layered materials to create atomically sharp, dangling-bond-free interfaces inaccessible in conventional epitaxial semiconductor stacks. This lattice-mismatch-free assembly enables fabrication of high-performance FETs with superior electronic and optoelectronic behavior compared to bulk counterparts.
The dominant material systems in this dataset are transition metal dichalcogenides — principally MoS₂, WS₂, WSe₂, MoTe₂, MoSe₂, SnSe₂, and HfSe₂ — stacked vertically or integrated laterally, often with hexagonal boron nitride as the gate dielectric and graphene as a transparent electrode. A secondary class involves 2D/3D heterojunctions pairing TMDs with silicon or GaN.
Four key sub-technology clusters are identified in the dataset: vertical 2D/2D tunnel FETs (TFETs) achieving sub-60 mV/dec subthreshold swings; ultrashort vertical channel FETs with spacer-defined sub-10 nm geometries; 2D/3D hybrid and organic-inorganic heterostructure FETs; and reconfigurable threshold-switching FETs exploiting bipolar TMD transport.
Among retrieved records, China accounts for at least 20 distinct CN-jurisdiction patents in this dataset, filed across universities and research institutes. US and WO filings in this dataset concentrate on scalable fabrication methods such as dative epitaxy and novel device architectures, including contributions from KAIST, SUNY Research Foundation, and the National University of Singapore.
Innovation Phases: From Proof-of-Concept to Manufacturing
The retrieved dataset reveals three distinct innovation phases: conceptual establishment (2014–2015), performance validation (2016–2023), and manufacturing-oriented filings (2024–2026). Patent and literature activity accelerated notably from 2020 onward as room-temperature BTBT demonstrations and vertical scaling milestones were achieved.
CN vs. US/WO Patent Filing Distribution by Assignee Type — Dataset Snapshot
In this dataset, Chinese-jurisdiction assignees account for at least 20 distinct patent records concentrated across universities and research institutes, while US/WO filings are fewer but target scalable fabrication and broad architectural claims.
↗ Click bars to explorevdW Heterostructure Transistor Records by Innovation Phase (Dataset Snapshot)
In this dataset, filing and publication activity shows clear acceleration from the 2020–2023 performance validation phase onward, with 2024–2026 frontier filings introducing manufacturing-oriented architectures such as dative epitaxy and organic-inorganic hybrid FETs.
↗ Click bars to exploreKey Application Areas for vdW Heterostructure Transistors
The retrieved dataset identifies five primary application domains spanning ultra-low-power logic, infrared photodetection, optoelectronic emitters, spintronic devices, and solar energy conversion. Each domain is supported by specific patent filings or literature demonstrations traceable to named assignees or documented device performance.
Ultra-Low-Power Post-CMOS Logic
The dominant application target in this dataset is ultra-low-power logic benchmarked against the 60 mV/dec Boltzmann limit of conventional MOSFETs. A vertical WSe₂/SnSe₂ TFET demonstrated a point subthreshold swing of 35 mV/dec and on/off ratio greater than 10⁵, co-integrated with a MOSFET on the same WSe₂ flake (2020). KAIST’s 2D-3D HJ-TFET patent family explicitly targets complementary CMOS replacement and Moore’s law extension (US, 2021).
Low-Power LogicInfrared and Broadband Photodetection
Multiple patents target near-infrared and telecom-wavelength photodetection using vdW architectures. The Shanghai Institute of Technical Physics (Chinese Academy of Sciences) filed a US-active patent in 2024 on a fully depleted n-p-n sandwich vdW infrared photodetector with improved photo-carrier separation and reduced dark current. Waveguide-integrated MoTe₂/graphene vertical heterostructure photodetectors achieved bandwidth ≥24 GHz at telecom wavelengths on silicon photonics platforms (2020).
PhotodetectionSpintronic and Topological Devices
The ZrTe₂/CrTe₂ vdW heterostructure provides a wafer-scale platform combining 2D ferromagnetism and topological semimetal properties, documented in a 2022 literature study. Giant topological Hall effects in CrTe₂/Bi₂Te₃ vdW heterostructures reveal pathways toward topological transistor concepts (2021). This application domain remains largely at the academic stage with minimal patent activity in this dataset, representing an early IP capture opportunity.
SpintronicsSolar Energy and Photocatalysis
The InSe/Te vdW heterostructure achieves a computed power conversion efficiency of 13.39% for solar cells (2021 literature). Jiangxi University of Science and Technology filed a 2025 CN patent covering a BlueP/gamma-GeS heterostructure with solar-to-hydrogen efficiency of 18.06%. East China Jiaotong University patented a dual-use alpha-In₂Se₃/GaS structure switchable between type-I emitter and type-II photovoltaic alignment via ferroelectric polarization (CN, 2024).
Solar EnergyKey Patent Assignees in vdW Heterostructure Transistors — Dataset Snapshot
In this dataset, Chinese universities and research institutes account for the largest share of CN-jurisdiction patent filings, with at least 20 records identified in retrieved records. US and WO filings are fewer in this dataset but include notable architectural and manufacturing-method patents from KAIST, the SUNY Research Foundation, and the National University of Singapore.
Top Patent Assignees by Filing Count — vdW Heterostructure Transistors (Dataset Snapshot)
↗ Click bars to exploreNational Center for Nanoscience
The National Center for Nanoscience and Technology (Beijing, China) holds at least two active CN-jurisdiction patents in this dataset, filed between 2018 and 2019. These cover asymmetric vdW heterostructure devices and a MoTe₂/MoS₂ vdW heterostructure FET achieving on/off ratio ~10⁷ and current rectification ratio ~10⁶ with dynamic polarity switching. Both patents are listed as active in retrieved records.
China — CNSUNY Research Foundation
The Research Foundation for the State University of New York holds two patents in this dataset covering hybrid covalent-van der Waals 2D heterostructures by dative epitaxy, filed as a WO publication (2023) and a US-pending application (2025). These patents address wafer-scale deposition of crystal layers on vdW templates including WSe₂, WS₂, MoS₂, and NbSe₂, targeting manufacturing scalability beyond laboratory-scale flake assembly.
United StatesFour Frontier Directions from 2023–2026 Filings
Based on filings and publications from 2023 to 2026 within this dataset, four emerging directions signal the transition from laboratory demonstration toward scalable, application-specific vdW heterostructure transistor platforms.
Dative Epitaxy for Wafer-Scale Manufacturing
The SUNY Research Foundation’s patent family on hybrid covalent-vdW 2D heterostructures by dative epitaxy (WO 2023, US-pending 2025) addresses the critical industrialization bottleneck of exfoliation-and-restacking by enabling epitaxial deposition on vdW templates including WSe₂, WS₂, MoS₂, and NbSe₂. This represents a shift from laboratory-scale flake devices to manufacturable wafer-scale processes. It is one of the clearest manufacturing-readiness signals in the 2024–2026 frontier filing cohort.
Reconfigurable Transistors for Logic-in-Memory
The bipolar WSe₂/Ta₂NiX₅ reconfigurable transistor (Nanjing University of Science and Technology, CN-pending 2024) exploits bipolar transport characteristics of WSe₂ stacked with Ta₂NiX₅ to realize devices controllable by bottom gate and source/drain bias, compatible with logic circuit integration without additional lithography. The National University of Singapore’s threshold switching FET (WO 2025) monolithically integrates a 2D vdW switching layer with the gate dielectric as a single entity, enabling steep-slope operation.
Vertical 2D/2D TFETs vs. Vertical Channel FETs: Key Dimensions
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| Dimension | Vertical 2D/2D TFET | Vertical Channel FET (VFET) |
|---|---|---|
| Operating Mechanism | Band-to-band tunneling (BTBT) through type-II or type-III aligned 2D/2D interfaces | Vertical current flow through atomically thin semiconductor channel defined by spacer thickness |
| Subthreshold Swing | 35 mV/dec (point) demonstrated in WSe₂/SnSe₂ system (2020) | Not specifically benchmarked for subthreshold swing in retrieved records |
| On/Off Ratio | >10⁵ demonstrated in WSe₂/SnSe₂ TFET (2020) | 10⁷–10⁹ demonstrated in monolayer CVD MoS₂ vertical FET (2019) |
| Channel Length Scaling | Defined by 2D layer thickness and band alignment; sub-10 nm feasible | Defined by insulating spacer thickness; 20 nm pitch demonstrated (2023) |
| Key Material Systems | WSe₂/SnSe₂, WS₂/SnS₂, GeSe/GeTe, MoS₂/h-BN stacks | CVD MoS₂ monolayer, hybrid Au/graphene drain contacts |
| On-Current Density | GeSe/GeTe simulated at 2320–2387 µA/µm (2022 simulation) | ~70 µA/µm demonstrated experimentally in MoS₂ vertical FET (2019) |
| Primary Application Target | Ultra-low-power logic; post-CMOS replacement | High-density integration; Moore’s law extension at sub-10 nm nodes |
| Key IP Holders (Dataset) | KAIST (US, 2021); National Center for Nanoscience and Technology (CN, 2019) | KAIST 2D-3D HJ-TFET patent family (US, 2021) |
Frequently Asked Questions: vdW Heterostructure Transistors
A point subthreshold swing of 35 mV/dec — below the 60 mV/dec Boltzmann limit of conventional MOSFETs — was demonstrated in a vertical WSe₂/SnSe₂ TFET co-integrated with a MOSFET on the same WSe₂ flake, as reported in a 2020 literature study included in this dataset.
The dominant material systems in this dataset are transition metal dichalcogenides including MoS₂, WS₂, WSe₂, MoTe₂, MoSe₂, SnSe₂, and HfSe₂, often stacked with hexagonal boron nitride (h-BN) as the gate dielectric and graphene as a transparent electrode. 2D/3D junctions pairing TMDs with silicon or GaN are a secondary class.
A vertical transistor pitch of 20 nm was demonstrated using a hybrid Au/graphene drain with sheet resistance of approximately 100 Ω/sq, as reported in a 2023 literature record within this dataset.
In this dataset, the National Center for Nanoscience and Technology (China), Hunan University (China), Korea Advanced Institute of Science and Technology (KAIST, US-jurisdiction), and the Research Foundation for the State University of New York each have two identified patent records. These counts reflect retrieved records only and should not be interpreted as comprehensive rankings of total global filing activity.
Dative epitaxy is a method for epitaxially depositing crystal layers on van der Waals templates such as WSe₂, WS₂, MoS₂, and NbSe₂, enabling wafer-scale 2D heterostructure fabrication without the exfoliation-and-restacking process used in laboratory-scale flake devices. The Research Foundation for SUNY filed patents on this approach (WO 2023, US-pending 2025) as documented in this dataset.
Beyond ultra-low-power logic, the dataset documents applications in infrared and telecom-wavelength photodetection (including a ≥24 GHz bandwidth MoTe₂/graphene device), optoelectronic light emitters with bias-tunable spectra, spintronics using ZrTe₂/CrTe₂ and CrTe₂/Bi₂Te₃ heterostructures, solar cells with computed efficiency of 13.39% (InSe/Te), and photocatalytic hydrogen generation with 18.06% solar-to-hydrogen efficiency (BlueP/gamma-GeS).
Data and insights on this page are based on a limited patent and literature dataset and are for reference only. Figures may not represent the complete technology landscape.