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VCO Phase Noise Reduction for Radar — PatSnap Eureka

VCO Phase Noise Reduction for Radar — PatSnap Eureka
VCO Phase Noise · Radar Signal Generation

Reducing Phase Noise in Voltage-Controlled Oscillators for High-Precision Radar

Phase noise in VCOs is a critical limiting factor in radar receiver sensitivity, angular resolution, and maximum detection range. This analysis draws on more than 40 patents and research publications to map the state of the art — from LC tank bypass circuits to real-time system-level compensation.

VCO Phase Noise Performance Benchmarks: ISF-shaped CMOS −138.4 dBc/Hz, Class-C Bias Cal −124.1 dBc/Hz, High-PD-Freq PLL −121 dBc/Hz at 100 kHz, External High-Q +10 dB improvement Phase noise performance figures from key VCO noise reduction techniques identified in 40+ patents and publications via PatSnap Eureka. Lower values indicate better performance; the ISF-shaped LC cross-coupled oscillator from Babol Noshirvani University achieves the best reported figure at −138.4 dBc/Hz at 1 MHz offset in 0.18 µm CMOS. −138 −132 −126 −122 −116 −138.4 ISF-Shaped 0.18µm CMOS −124.1 Class-C Bias 28nm CMOS −121 High PD-Freq PLL 4.5 GHz +10 dB Ext. High-Q Network Phase Noise (dBc/Hz)
40+
Patents & publications analysed
−138.4
dBc/Hz best reported phase noise at 1 MHz offset
10 dB
Phase noise improvement from external high-Q network
8+
Major industrial assignees including IBM, Intel, Raytheon
Circuit-Level Design

LC Tank Optimization and Resonator Enhancement

The quality factor of the LC tank circuit is the primary determinant of close-in phase noise. Researchers and patent filers have developed complementary approaches to raise effective Q and suppress noise injection from active devices.

IBM Patent Architecture

Noise Bypass Circuits in Parallel with the LC Tank

As described in IBM's 2018 patent, a bypass circuit placed in parallel with the tank creates a low-impedance path at a frequency approximately twice the oscillator frequency. This immunizes the oscillator core from external supply noise and reduces noise contribution from the cross-coupled semiconductor devices forming the negative resistance. IBM filed multiple continuations of this architecture, with active patents spanning 2016 through 2020, reflecting sustained IP prosecution of a core architectural innovation.

Most extensively patented IBM VCO technique
CMOS Topology

Complementary NMOS/PMOS with Three-Stage Capacitive Tuning

The University of Science and Technology of China's 2021 digitally controlled oscillator employs a complementary differential MOS compensation circuit providing negative resistance to sustain tank oscillation. A three-stage capacitive tuning array covers coarse, medium, and fine frequency adjustment. An LC filter circuit within the design diverts thermal noise to ground through capacitors while using inductors to present high impedance to flicker noise currents — directly addressing the two dominant close-in noise mechanisms in CMOS VCOs.

Dual thermal + flicker noise suppression
Transistor Operating Region

ISF Shaping via Transistor Operating-Region Management

Research from Babol Noshirvani University of Technology (2020) demonstrates that by reducing closed-loop gain at zero-crossing points — where transistor noise injection is most damaging — and repositioning high gain to non-zero-crossing intervals, the impulse sensitivity function (ISF) of the oscillator can be shaped. This achieves −138.4 dBc/Hz at 1 MHz offset at 900 MHz in 0.18 µm CMOS. A complementary current-shaping feedback injection approach from Universidad de Las Palmas de Gran Canaria uses only two additional transistors with negligible area penalty in 90 nm CMOS.

−138.4 dBc/Hz at 1 MHz in 0.18 µm CMOS
Wideband VCO Design

Coupled Microstrip Resonator Networks for Broadband Applications

Synergy Microwave Corporation's 2020 patent employs a plurality of microstrip resonators coupled together into a coupled-resonator network, with a tuning network that adjusts the inter-resonator coupling rather than loading the resonator directly. This hybrid coarse/fine tuning strategy avoids the additional noise and loading normally imposed by a separate fine-tuning varactor network — a well-known source of phase noise degradation in wideband VCOs operating over ranges such as 1200–3600 MHz. The AESA Radar Research Center at Hanwha Thales validated broadband resonator-based noise suppression through simulation, fabrication, and measurement for radar front-end applications.

1200–3600 MHz broadband coverage
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Data Visualisation

Phase Noise Performance and Innovation Landscape

Key performance benchmarks and patent distribution across the VCO phase noise reduction ecosystem, drawn from 40+ sources analysed via PatSnap Eureka.

Phase Noise Benchmarks by Technique (dBc/Hz at 1 MHz offset)

ISF-shaped LC cross-coupled oscillators achieve the best reported close-in phase noise at −138.4 dBc/Hz, followed by PVT-insensitive Class-C bias calibration at −124.1 dBc/Hz.

Phase Noise Benchmarks by Technique: ISF-Shaped CMOS −138.4 dBc/Hz, Class-C Bias Cal −124.1 dBc/Hz, High PD-Freq PLL −121 dBc/Hz, External High-Q +10 dB improvement, Ultra-low PN PLL −116 dBc/Hz at 1 kHz Comparison of phase noise performance figures across five VCO noise reduction techniques identified from patent and literature analysis via PatSnap Eureka. All values are at 1 MHz offset unless otherwise noted. Lower dBc/Hz values indicate better phase noise performance. −138 −132 −126 −122 −116 −138.4 ISF-Shaped CMOS −124.1 Class-C Bias Cal −121 High PD-Freq PLL 4.5GHz −116 Ultra-Low PN PLL @1kHz −192.2 FOM Class-C VCO Phase Noise Technique

Patent & Publication Distribution by Assignee Type

US industrial assignees (IBM, Intel, Raytheon, MediaTek, ZeroG) account for the largest share, with growing contributions from Chinese and European academic institutions.

VCO Phase Noise Patent Distribution: US Industrial 45%, Asian Industrial and Radar 25%, Chinese University 18%, European and Other Academic 12% Distribution of 40+ VCO phase noise reduction patents and publications by assignee category, analysed via PatSnap Eureka. US industrial assignees including IBM, Intel, Raytheon, MediaTek, and ZeroG dominate with 45% of filings. 40+ Sources US Industrial (45%) Asian Industrial (25%) Chinese Univ. (18%) European Acad. (12%)

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System-Level Techniques

PLL Feedback Control and Power Supply Noise Rejection

Phase-locked loops remain the dominant system-level tool for phase noise reduction in radar signal chains. The PLL's feedback loop suppresses VCO phase noise within its bandwidth by referencing the VCO output to a low-noise reference oscillator. Intel Corporation addressed loop optimization through a closed-loop algorithmic approach: a noise power meter monitors the control voltage fed into the VCO and uses its noise power as a proxy for VCO phase noise within the loop bandwidth. A minimization algorithm then iterates over adjustable VCO parameters without requiring external phase noise measurement instrumentation.

For FMCW radar applications, Hyundai Mobis's 2015 patent demonstrates that rapid frequency sweeping prevents conventional fixed-bandwidth PLLs from achieving phase noise optimization at each tuning step. A variable loop filter dynamically adjusted to maintain optimal phase noise characteristics is essential for achieving angular resolution and maximum detection range targets. A high-phase-detection-frequency architecture demonstrated phase noise of better than −116 dBc/Hz at 1 kHz, −120 dBc/Hz at 10 kHz, and −121 dBc/Hz at 100 kHz at a 4.5 GHz output — performance directly applicable to modern radar signal generators. The IEEE has extensively documented PLL noise trade-offs in radar synthesizer design.

Supply voltage noise is one of the most insidious sources of VCO phase noise degradation in practical radar hardware. Low-frequency (sub-kHz) noise components couple through the VCO supply rail and modulate the oscillation frequency, creating close-in phase noise sidebands that are particularly harmful for moving-target-indicator (MTI) and synthetic aperture radar (SAR) applications. Electronics and Telecommunications Research Institute (ETRI) developed an active rejection approach using negative feedback through a closed transistor loop to cancel supply noise before it reaches the oscillator core, achieving substantially better PSRR than passive filtering alone. MediaTek's current-biased VCO topology similarly demonstrates higher rejection of common-mode supply disturbances compared to voltage-biased designs.

SAAB AB's 2022 monostatic radar system incorporates a dedicated phase noise controller with an ADC that duplicates, delays, and mixes the RF oscillator signal to extract a decorrelated phase noise estimate, enabling real-time active compensation within the radar signal processing chain. Infineon Technologies' 2020 radar device patent uses artificial radar targets for decorrelated phase noise extraction, confirming that system-level real-time estimation is now being integrated at the architecture level. According to ITU radar spectrum regulations, phase noise performance directly impacts adjacent-channel interference and detection sensitivity.

−116
dBc/Hz at 1 kHz offset, high-PD-freq PLL at 4.5 GHz
−120
dBc/Hz at 10 kHz offset, same 4.5 GHz source
−121
dBc/Hz at 100 kHz offset, applicable to radar signal generators
5
Active IBM US patents on noise bypass circuit architecture
Key Radar Assignees
  • Infineon Technologies AG — radar phase noise estimation
  • SAAB AB — monostatic radar phase noise controller
  • Hyundai Mobis — FMCW adaptive PLL optimization
  • Hanwha Thales (AESA) — broadband radar front-end VCO
  • Raytheon Company — amplitude noise reduction for ultra-low PN
Search Radar VCO Patents
Bias Calibration & Innovation Clusters

Bias Current Calibration and Key Industry Players

Production-scalable bias calibration and the distinct innovation clusters driving VCO phase noise reduction across industry and academia.

⚙️

ZeroG Wireless Bias Current Calibration

ZeroG Wireless (now Silicon Laboratories) developed a hardware calibration circuit that monitors the average common-mode node voltage of the VCO while sweeping the bias current. The bias current producing the minimum average common-mode voltage is identified as the optimal phase noise operating point and applied as the permanent bias — removing the need for manual characterization and enabling production-level noise optimization across three active US patents (2008, 2010).

🎯

PVT-Insensitive Class-C Calibration (GIST 2022)

A 28 nm CMOS implementation from Gwangju Institute of Science and Technology demonstrates automatic calibration that locates the minimum phase noise bias point regardless of process-voltage-temperature (PVT) variation, achieving −124.1 dBc/Hz at 1 MHz offset at 4.3 GHz with a figure of merit of −192.2 dBc/Hz and a chip area of only 0.196 mm². This represents the state of the art in production-scalable CMOS VCO noise optimization. See the PatSnap customer success stories for R&D applications of this scale.

🔒
Unlock Raytheon AM-noise & Chinese University cluster analysis
Discover how amplitude noise limits ultra-low-phase-noise oscillators and the emerging CMOS VCO patent landscape from leading Chinese universities.
Raytheon RF bridge technique AM-to-PM conversion risk 5 Chinese university assignees + more
Access Full Analysis on Eureka →
Design Framework

Five-Layer VCO Phase Noise Reduction Strategy for Radar

The dominant technical approaches observed across the patent and literature data fall into five major categories, each addressing a distinct noise pathway in the VCO signal chain.

Five-Layer VCO Phase Noise Reduction Strategy: 1. LC Tank Q Optimization, 2. Resonator Enhancement, 3. PLL Loop Bandwidth Control, 4. Power Supply Noise Rejection, 5. Bias Current Calibration Sequential five-layer design framework for VCO phase noise reduction in radar applications, derived from patent and literature analysis via PatSnap Eureka. Each layer targets a distinct noise pathway from the oscillator core to the system output. 1 LC Tank Q Optimization 2 Resonator Enhancement 3 PLL Loop BW Control 4 Supply Noise Rejection 5 Bias Current Calibration Radar Output

Technique-by-Technique Performance & Assignee Reference Table

🔒
Unlock the full technique-assignee performance table
See all 10+ techniques with assignee, performance metrics, frequency band, and CMOS node — mapped from 40+ patents.
Bias calibration benchmarks AM-noise reduction data PLL frequency source specs + more
View Full Table on Eureka →

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Frequently asked questions

VCO Phase Noise for Radar — Key Questions Answered

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References

  1. Study on Improving the Phase Noise of Broadband Voltage-Controlled Oscillator — AESA Radar Research Center, Hanwha Thales, 2016
  2. Phase-noise Reduction Through an External High-Q Network Using a Black-Box Oscillator Model — DICOM, University of Cantabria, 2021
  3. Phase noise reduction in voltage controlled oscillators — International Business Machines Corporation, 2018
  4. Phase noise reduction in voltage controlled oscillators — International Business Machines Corporation, 2016
  5. Phase noise reduction in voltage controlled oscillators — International Business Machines Corporation, 2020
  6. Phase noise reduction in voltage controlled oscillators — International Business Machines Corporation, 2018
  7. Low Noise, Hybrid Tuned Wideband Voltage Controlled Oscillator — Synergy Microwave Corporation, 2020
  8. Phase Noise Minimized Phase/Frequency-Locked Voltage-Controlled Oscillator Circuit — Intel Corporation, 2011
  9. Phase Noise Minimized Phase/Frequency-Locked Voltage-Controlled Oscillator Circuit — Palaskas, Yorgos, 2008
  10. Phase Noise Optimization Apparatus and Method — Hyundai Mobis, 2015
  11. Calibration of Voltage Controlled Oscillators — ZeroG Wireless, Inc., 2008
  12. Calibration of voltage controlled oscillators — ZeroG Wireless, Inc., 2010
  13. Amplitude-Noise Reduction System and Method for Ultra-Low Phase-Noise Oscillators — Raytheon Company, 2018
  14. Radar Device with Phase Noise Estimation — Infineon Technologies AG, 2020
  15. A Monostatic Radar System — SAAB AB, 2022
  16. Voltage-Controlled Oscillator Robust Against Power Noise — Electronics and Telecommunications Research Institute, 2010
  17. Low-Noise Voltage-Controlled Oscillator Circuit — Nippon Dempa Kogyo, 2012
  18. A New Current-Shaping Technique Based on a Feedback Injection Mechanism to Reduce VCO Phase Noise — Universidad de Las Palmas de Gran Canaria, 2021
  19. A Phase Noise Reduction Technique in LC Cross-coupled Oscillators with Adjusting Transistors Operating Regions — Babol Noshirvani University of Technology, 2020
  20. A PVT-Insensitive Optimal Phase Noise Point Tracking Bias Calibration in Class-C VCO — Gwangju Institute of Science and Technology, 2022
  21. Low-power, Large-bandwidth, High-resolution, Low-phase-noise Digitally Controlled Oscillator — University of Science and Technology of China, 2021
  22. A Design of Ultra-low Phase Noise Frequency Source Based on High Phase Detection Frequency, 2019
  23. RF Voltage-Controlled Oscillator and Design Method — MediaTek Inc., 2008
  24. Crystal oscillator and phase noise reduction method thereof — MediaTek Inc., 2022
  25. IEEE — Institute of Electrical and Electronics Engineers (PLL and VCO noise standards)
  26. ITU — International Telecommunication Union (Radar spectrum and phase noise regulations)
  27. EPO — European Patent Office (VCO and oscillator patent filings database)

All data and statistics on this page are sourced from the references above and from PatSnap's proprietary innovation intelligence platform.

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